On-Chip Encryption Circuit Parallel Memory Access
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Solution Overview
Problem
High-performance processors with large-scale circuits and external memory require secure data encryption to protect access and ensure security, but existing solutions increase memory access time due to encryption and decryption processes.
Innovation Solution
Incorporating an encryption/decryption circuit within a chip that uses a common key in CTR mode for encrypting and decrypting data signals, allowing for secure data processing while minimizing the impact on memory access time by performing encryption and decryption in parallel with memory operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data encryption is performed using existing solutions, then security is improved, but memory access time increases
Solution Approach 1:
The encryption circuit is merged with the memory controller onto the same chip, creating an integrated security-memory system. This integration allows encryption and decryption operations to be performed concurrently with memory access operations, eliminating the sequential processing delay that would otherwise occur and thereby reducing memory access time while maintaining security.
Solution Approach 2:
The encryption key is pre-loaded into the encryption circuit before memory access operations begin. This preliminary preparation of cryptographic materials allows the encryption/decryption process to proceed in parallel with memory operations without waiting for key setup, thus reducing overall access time while ensuring secure data protection.
2Reliability
If an encryption circuit is added to the processor chip, then data security is improved, but device complexity increases
Solution Approach 1:
The encryption circuit is combined with the memory controller on the same chip, creating a unified integrated circuit that performs both memory management and cryptographic operations. This merging approach consolidates functionality rather than adding separate discrete components, thereby improving security while minimizing the increase in overall device complexity.
3Loss of time
If parallel encryption and memory operations are performed, then memory access time is reduced, but device complexity increases
Solution Approach 1:
The encryption circuit and memory controller are merged into a single integrated unit, sharing common resources such as the data bus and control logic. This integration enables parallel operation of encryption and memory access functions while avoiding the complexity overhead of completely separate systems, as the merged design efficiently coordinates both operations through shared infrastructure.
Solution Approach 2:
The integrated circuit is designed to perform multiple functions: memory control operations and encryption/decryption operations. This multi-functionality allows the same hardware resources to be utilized for both memory management and cryptographic processing, enabling parallel operations without proportionally increasing device complexity, as the circuit is engineered to handle diverse operations through unified control mechanisms.
Data Source
AI summary
A device is provided which includes: a processor that outputs a command signal or an address signal and includes a bus module which inputs or outputs a data signal; and an encryption circuit that encrypts or decrypts the data signal in an encryption method using a common key and the address signal, wherein the processor and the encryption circuit are provided in a chip.