On-Chip Eye-Pattern Asymmetry Testing for I/O Circuit Matching
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Solution Overview
Problem
High-performance input/output (I/O) circuits face challenges in accurate impedance matching and balancing, leading to performance degradation due to manufacturing deviations, which are costly and time-consuming to test, especially as circuits become more complex and are often not detectable until integrated into larger systems.
Innovation Solution
An integrated circuit with a transmitter, receiver, and control logic that assesses asymmetry in eye patterns during an asymmetry testing mode, generating and analyzing eye patterns to determine remedial actions, allowing for on-chip testing and potential repair or replacement before system shipment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If qualification testing is performed during or immediately after manufacturing to identify deviations in component values, then manufacturing precision is improved, but testing time and cost increase significantly
Solution Approach 1:
The I/O circuit performs self-diagnosis by using its own transmitter and receiver components to generate eye patterns and detect asymmetries. The circuit tests itself without requiring external testing equipment, thereby reducing testing time and cost while maintaining manufacturing precision requirements
Solution Approach 2:
The testing functionality is extracted as a separate asymmetry detection mode that can be independently activated. The control logic separates normal operation from testing operation, allowing the circuit to perform qualification testing only when needed without affecting normal operation time
2Manufacturing precision
If qualification testing is performed during or immediately after manufacturing, then manufacturing precision is improved, but device complexity increases due to testing requirements
Solution Approach 1:
The transmitter and receiver components serve dual purposes: they function as normal I/O components during operation and as testing components during asymmetry detection mode. This multi-functionality eliminates the need for separate dedicated testing circuitry, reducing device complexity while maintaining testing capability
Solution Approach 2:
The testing functionality is merged with the normal I/O circuit operations. The same physical components (transmitter, receiver, communication channel) are used for both data transmission and asymmetry testing, consolidating functions and reducing overall device complexity
3Reliability
If proper testing is performed after circuit integration into a larger system, then reliability is improved, but testing time is delayed significantly
Solution Approach 1:
The asymmetry detection capability is built into the circuit during manufacturing, allowing testing to be performed preliminarily at any time before system integration. This eliminates the delay of waiting for system integration while ensuring reliability through early detection of component deviations
4Ease of manufacture
If asymmetry testing is performed without external testers using on-chip components, then ease of manufacture is improved, but measurement precision may be compromised
Solution Approach 1:
The eye pattern serves as an intermediary representation of the signal characteristics. By analyzing the geometric properties of the eye pattern generated by the communication channel, the system can indirectly measure asymmetries with high precision using only on-chip components, bridging the gap between ease of manufacture and measurement precision
Data Source
AI summary
During an asymmetry testing mode of an integrated circuit, the asymmetry of an on-chip I/O circuit is tested. In particular, a transmitter circuit in the integrated circuit transmits electrical signals, which are associated with a predefined data pattern, to a receiver circuit in the integrated circuit via a communication channel (such as a differential pair of signal lines). Then the integrated circuit generates an eye pattern using the received electrical signals, and determines an asymmetry of the eye pattern about a common reference level of the received electrical signals. Furthermore, the integrated circuit performs remedial action based on the determined asymmetry. For example, the integrated circuit may compare the determined asymmetry with a predefined asymmetry criterion and, if the asymmetry exceeds the predefined asymmetry criterion, may output a result of the comparison that indicates a failure of the asymmetry test.