On-Chip Eye Diagram Capture for CoWoS Signal Monitoring
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Solution Overview
Problem
In three-dimensional integrated circuit (3D-IC) technology, particularly for chip-on-wafer-on-substrate (CoWoS) applications, conventional methods fail to display eye diagrams due to high signal speeds, limited chip area, and lack of controlled collapse chip connection (C4) solder bump resources, making it difficult to monitor bus eye diagrams and fine-tune analog performance parameters.
Innovation Solution
An on-chip eye diagram capture device system that includes a phase-locked loop, digitally controlled delay line, edge detection circuit, and voltage threshold comparator, allowing for time-delayed digital signals and voltage comparisons to determine eye width and height, enabling eye diagram capture and analysis within the chip without external connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional external oscilloscope connection methods are used, then eye diagrams can be displayed for signal quality evaluation, but high-speed IO performance is impacted and chip area is consumed for bonding out signals
Solution Approach 1:
The patent merges the eye diagram measurement functionality directly into the chip by integrating a delay line, edge detection circuits, and logic analysis capabilities within the semiconductor device. This consolidation eliminates the need for external oscilloscope connections and bonding out high-speed IO signals, thereby preserving high-speed IO performance while maintaining eye diagram measurement capability.
Solution Approach 2:
The patent transitions the measurement approach from external physical connection (spatial dimension) to internal temporal sampling (time dimension). By using a delay line to create time-delayed copies of digital signals and performing edge detection in the time domain, the system captures eye diagram information without requiring external hardware connections, thus avoiding impact on high-speed IO performance.
2Measurement precision
If C4 solder bump resources are allocated for monitoring bus eye diagrams, then signal quality can be evaluated, but available C4 resources and chip area are reduced
Solution Approach 1:
The patent implements a multi-functional integrated circuit that performs both normal digital signal processing and eye diagram measurement functions using the same chip resources. The delay line and edge detection circuits can operate concurrently with the main device functionality, eliminating the need for dedicated C4 solder bumps solely for measurement purposes.
Solution Approach 2:
The device performs self-measurement by incorporating measurement functionality within the chip itself. The integrated delay line, edge detection circuits, and logic analysis capabilities enable the device to monitor its own signal quality without requiring external measurement infrastructure or additional C4 resources, thereby preserving chip area for other purposes.
3Measurement precision
If high-speed IO signals are bonded out for eye diagram display, then signal quality evaluation is possible, but high-speed IO performance for normal operation is degraded
Solution Approach 1:
The patent segments the measurement function from the high-speed IO function by creating a separate internal measurement pathway. The delay line extracts and processes copies of the digital signals for eye diagram analysis, while the original high-speed IO signals remain dedicated to their primary function. This segmentation allows independent optimization of both measurement accuracy and signal speed.
Solution Approach 2:
The patent introduces an intermediary measurement system within the chip that acts as a mediator between the high-speed IO signals and the analysis function. The internal delay line and edge detection circuits serve as intermediaries that capture signal characteristics without requiring the high-speed IO signals to be physically bonded out, thus maintaining signal integrity and performance while enabling measurement.
Data Source
AI summary
A system for capturing an eye diagram is disclosed. In various embodiments, the system includes: a delay line arranged to receive a digital signal and output a time delayed version of the digital signal; an edge detection circuit arranged to receive the digital signal and the time delayed version of the digital signal, the edge detection circuit operating to output a signal corresponding to a logical value of the digital signal received coincident with an edge of the time delay version of the digital signal; a voltage comparator arranged to receive the digital signal and a reference voltage, the voltage comparator operating to output a first signal when a voltage of the digital signal and the reference voltage are equal to each other; and a controller that includes: an edge detection circuit receiver connected to receive the output signal from the edge detection circuit; a delay line control circuit connected to provide a delay time control signal to the delay line; a voltage comparator receiver connected to receive the first signal from the voltage comparator; and a voltage control unit connected to provide a controlled voltage to the voltage comparator.