On-Chip Fault Injection Module for Processor Core Testing

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Solution Overview

Problem

Existing fault injection simulation methods struggle with achieving realistic testing on full systems due to difficulties in simulating peripheral interactions and slow debugger connections, leading to inefficient and time-consuming testing processes.

Innovation Solution

A device under test (DUT) is equipped with an on-device fault injection (FI) module that executes fault injection testing on a processor core through a debug module, utilizing a debug port and transport module to translate and control debug signals, and includes a multiplexer for selective connection to the processor core, enabling efficient fault injection and analysis.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If fault injection simulation is performed on a full system with peripherals, then testing coverage is improved, but testing complexity and difficulty increase significantly

Engineering Contradiction:

Improvetesting coverageVSAvoidtesting complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent segments the fault injection testing by focusing exclusively on the processor core through the debug module, separating it from peripheral interactions. This allows fault injection testing to be performed on the core without requiring the full system context, thereby reducing testing complexity while maintaining core functionality coverage.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent extracts the processor core from the full system context and enables fault injection testing on the core independently through the debug module. By taking out the core from the complete system environment, the patent allows simplified fault injection testing that doesn't require peripheral interactions, thus reducing overall testing complexity.

Inventive Principle:

Principle #2Taking out (Extraction)

2Ease of operation

If a debugger is used for fault injection emulation, then fault injection capability is achieved, but connection speed and efficiency deteriorate

Engineering Contradiction:

Improvefault injection capabilityVSAvoidconnection speed

Core Design Contradiction:

Ease of operationVSSpeed

Solution Approach 1:

The patent introduces a dedicated debug module as an intermediary between the processor core and the fault injection mechanism. This debug module provides a direct interface for fault injection without requiring the full debugger system, thereby achieving fault injection capability while improving connection speed and efficiency.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Measurement precision

If complex fault modelling is implemented, then fault injection accuracy is improved, but testing time increases exponentially

Engineering Contradiction:

Improvefault injection accuracyVSAvoidtesting time

Core Design Contradiction:

Measurement precisionVSLoss of time

Solution Approach 1:

The patent applies local quality by implementing fault injection mechanisms tailored to specific processor core operations and instructions rather than attempting to model all possible faults across the entire system. This allows accurate fault injection for critical operations while avoiding the time-consuming complexity of comprehensive fault modelling.

Inventive Principle:

Principle #3Local quality

Data Source

PatentEP4575803A1Device under test, fault injection testing system and method for fault injection testing using an on-chip fault testing module

Publication Date: 2025.06.25 NXP BV

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AI summary

There is provided, in one embodiment, a device under test, fault injection (FI) testing system and method for FI testing that uses an on-device FI module operable to execute FI testing on a processor core on the device under test through a debug module. The device under test includes a debug port designed to receive external protocol-specific debug signals and a debug transport module connected to the debug port. The debug module is connected to the debug transport module to receive the core-specific debug signals.