On-Chip Gate Resistor Layout for Damped MOSFET Switching
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Solution Overview
Problem
Existing power semiconductor devices face challenges in efficiently incorporating lumped gate resistors on-chip to manage gate resistance and reduce switching losses, particularly in cascoded configurations with MOSFETs, while maintaining balanced performance across the chip.
Innovation Solution
Incorporating a lumped gate resistor using the sheet resistance of an implanted wide band-gap semiconductor material region, such as silicon carbide, between the gate pad and gate bus, which is formed during existing fabrication processes, thereby adding minimal overhead area and providing adjustable resistance values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If discrete gate resistors are added to the gate structure, then gate resistance is increased to reduce voltage overshoots and improve switching behavior, but device complexity and part count increase
Solution Approach 1:
The gate resistor is merged with the gate bus structure by forming a semiconductor layer directly on the gate bus. This integration eliminates the need for separate discrete gate resistor components, reducing part count while maintaining the desired gate resistance value for controlling voltage overshoots and improving switching behavior.
Solution Approach 2:
The semiconductor layer serves multiple functions: it provides the required gate resistance for damping switching transients, acts as part of the gate bus electrical connection, and can be formed using existing fabrication processes. This multi-functionality reduces overall device complexity while achieving the reliability improvements.
2Loss of energy
If lumped gate resistors are integrated on-chip, then switching losses are reduced and voltage overshoots are damped, but fabrication process complexity increases
Solution Approach 1:
The semiconductor layer is formed on the gate bus during preliminary fabrication steps before final device assembly. This preliminary action allows the gate resistor to be integrated early in the manufacturing process, reducing switching losses without requiring additional complex fabrication steps later in the process.
Solution Approach 2:
The gate resistance value is controlled by adjusting semiconductor layer parameters such as thickness, doping concentration, and material composition. These parameter changes allow optimization of switching losses and voltage overshoot damping while using standard fabrication techniques, maintaining ease of manufacture.
3Reliability
If the gate resistance is increased by adding semiconductor material, then transient effects are damped and switching performance improves, but chip area increases
Solution Approach 1:
Instead of increasing chip area by adding lateral extensions or separate resistor structures, the gate resistor is formed by adding a vertical semiconductor layer dimension on top of the gate bus. This dimensional approach achieves the required resistance value without increasing the lateral chip footprint, maintaining compact device geometry.
Solution Approach 2:
The semiconductor layer forming the gate resistor is nested within the existing gate bus structure. This nesting approach allows the gate resistance function to be embedded within the already-present gate bus area, achieving improved switching performance without requiring additional chip area beyond what is already allocated for the gate structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances gate resistance, reduces voltage overshoots, and improves switching performance by damping transient effects, while maintaining balanced chip operation and reducing part count.
Implementation Method 1
The gate structure has a distributed gate resistance, which is a function of the length of the electrical path from the gate bond pad (or other gate terminal) to the gate finger of each individual unit cell, the lengths of the gate fingers, and the sheet resistance of the materials forming the gate structure.
Data Source
AI summary
Power semiconductor devices comprise a gate pad, a gate bus, and a gate resistor that is electrically interposed between the gate pad and the gate bus and comprises a wide band-gap semiconductor material region.