On-Chip Harmonic Filtering Circuit With Tunable Impedance Matching

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Solution Overview

Problem

Existing wireless RF communication devices rely on external harmonic rejection filters, which increase cost and size due to the need for off-chip components, while on-chip tunable passive techniques for harmonic filtering are not easily implementable due to low quality (Q) factors and lack of tunability.

Innovation Solution

An on-chip harmonic filtering and matching circuit is introduced, utilizing a first capacitance in parallel with a first inductance, a second inductance, and a variable second capacitance, where the variable capacitance is controlled for both impedance matching and filtering, allowing for coarse and fine-tuning adjustments to achieve effective harmonic rejection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If off-chip harmonic rejection filters are used, then filtering performance is improved, but device size and cost increase

Engineering Contradiction:
Improvefiltering performanceVSAvoiddevice size
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent combines the harmonic rejection filtering function with the impedance matching network into a single integrated on-chip circuit. The matching network, which already connects the power amplifier to the antenna, is configured to simultaneously provide both impedance matching and harmonic filtering by utilizing resonant circuits formed with on-chip inductors and capacitors, eliminating the need for separate off-chip filter components.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent extracts the filtering function from the external off-chip domain and integrates it directly into the on-chip power amplifier output stage. By incorporating resonant circuits within the semiconductor device, the harmful harmonic frequencies are filtered out at the source without requiring external filter components, thereby reducing device size while maintaining filtering performance.

Inventive Principle:
Principle #2Taking out (Extraction)

2Area of stationary object

If on-chip harmonic filtering is implemented, then device size is reduced, but filtering effectiveness deteriorates due to low Q factors

Engineering Contradiction:
Improvedevice sizeVSAvoidfiltering effectiveness
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The patent merges multiple filtering stages and resonant circuits within the on-chip matching network to achieve cumulative filtering effectiveness. By combining the filtering actions of multiple on-chip resonant circuits operating at different harmonic frequencies, the system compensates for individual low Q factors and achieves overall effective harmonic rejection despite the inherent limitations of on-chip components.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution enables on-chip tunable filtering, reducing the need for external filters, improving RF communication performance by filtering harmonics such as third harmonics, while maintaining impedance matching, thus reducing device size and cost.

Implementation Method 1

The variable second capacitance is controlled to provide filtering with respect to an RF signal

Methodology Applied
Scientific EffectHarmonic filtering: Filter (electronic)

Implementation Method 2

The variable second capacitance is controlled to provide impedance matching with respect to a load coupled to the connection pad

Methodology Applied
Scientific EffectImpedance matching: Capacitance

Data Source

PatentUS10658999B1On-chip harmonic filtering for radio frequency (RF) communications
Publication Date: 2020.05.19 SILICON LABORATORIES INC
  • US10658999B1 patent drawing
  • US10658999B1 patent drawing
  • US10658999B1 patent drawing

AI summary

Systems and methods are disclosed for on-chip harmonic filtering for radio frequency (RF) communications. A filtering and matching circuit for an integrated circuit includes a first capacitance coupled in parallel with a first inductance, a second inductance coupled to the first inductance, and a variable second capacitance coupled between the first and second inductance. The variable second capacitance is controlled to provide filtering with respect to the RF signal as well as impedance matching with respect to a load coupled to the connection pad. For one embodiment, the variable second capacitance includes a coarse-tune variable capacitor circuit and a fine-tune variable capacitor circuit. The coarse-tuning controls impedance matching, and the fine tuning controls a notch for the filtering. The load can be an antenna for the RF communications. The integrated circuit can include a receive path, a transmit path, or both.