On-Chip Hot Count Circuits for Non-Volatile Memory Wear Leveling
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Solution Overview
Problem
In non-volatile memory systems, maintaining hot counts for wear leveling across multiple blocks is resource-intensive and prone to loss due to power failures, especially in large memory arrays, which can lead to uneven wear and potential block failure.
Innovation Solution
Dedicated on-chip circuits manage hot counts independently of the controller, storing them in an overhead data area and updating them during erase operations, allowing for block disabling or condition modification to prevent overuse, thus reducing the burden on the controller and minimizing data corruption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the controller maintains hot counts for multiple blocks, then wear leveling can be achieved, but the controller becomes resource-intensive and prone to data loss during power failures
Solution Approach 1:
The patent extracts the hot count maintenance function from the controller and implements it in dedicated on-chip circuits within the memory device itself. This separation removes the burden from the controller while ensuring hot count data is stored non-volatilely in the memory array, preventing data loss during power failures.
Solution Approach 2:
The memory device performs self-monitoring of erase cycles through on-chip circuits that automatically update hot counts for each block. This self-service capability eliminates the need for external controller intervention, reducing controller complexity while maintaining reliable wear leveling information.
2Reliability
If hot counts are maintained in the controller, then wear leveling is possible, but power failures can cause loss of hot count data
Solution Approach 1:
The system performs preliminary action by storing hot count data non-volatilely in the memory array before any power failure can occur. The on-chip circuits continuously maintain these counts in a persistent storage location, ensuring data integrity regardless of power events.
Solution Approach 2:
The patent uses the memory array itself to store hot count data, treating the storage medium as a reusable resource that persists across power cycles. This approach replaces volatile controller memory with non-volatile memory cells that inherently retain data without requiring continuous power.
3Reliability
If the controller manages all wear leveling operations, then comprehensive block monitoring is achieved, but access times increase due to controller workload
Solution Approach 1:
The patent segments the wear leveling functionality by creating dedicated on-chip circuits for each plane or block group that independently maintain their own hot counts. This segmentation allows parallel operation and reduces the central controller's workload, thereby decreasing access times while maintaining comprehensive monitoring.
Solution Approach 2:
Hot counts are updated in advance during erase operations by on-chip circuits before the controller needs to make wear leveling decisions. This preliminary action provides the controller with ready-to-use information, eliminating the need for real-time analysis and reducing access delays.
Data Source
AI summary
A hot count records the number of erase operations experienced by a block. The hot count is stored in an overhead data area of the block and is updated by circuits located on the same substrate as the block. Where a memory has two or more planes, each plane has circuits for updating hot counts.