On-Chip Hot Count Circuits for Wear Leveling
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Solution Overview
Problem
In non-volatile memory systems, maintaining hot counts for wear leveling across multiple blocks is resource-intensive for controllers, leading to potential data corruption and reduced performance due to the need for frequent communication and resource allocation.
Innovation Solution
Dedicated on-chip circuits manage hot counts independently within the memory array, allowing the controller to focus on other functions while reducing the risk of data corruption by storing hot counts in an overhead data area and updating them without requiring controller resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the controller manages hot counts for wear leveling across multiple blocks, then wear leveling functionality is achieved, but controller resource consumption increases and performance decreases
Solution Approach 1:
The hot count management function is extracted from the controller and implemented as dedicated on-chip circuits within the memory device itself. This allows the controller to focus on host communication and data management while the on-chip circuits independently track erase cycles and manage wear leveling, resolving the resource conflict.
Solution Approach 2:
The memory device performs wear leveling management autonomously through on-chip circuits that automatically track hot counts and remap data without requiring controller intervention. This self-service approach eliminates the performance penalty of controller-managed wear leveling while maintaining reliability.
2Reliability
If hot counts are maintained in volatile memory in the controller, then wear leveling can be performed, but data loss occurs during power outages
Solution Approach 1:
Hot count data is preliminarily stored in non-volatile overhead areas of the memory device before any wear leveling operations occur. This ensures that even if power is lost, the erase cycle counts are preserved and can be recovered after power restoration, preventing data loss.
Solution Approach 2:
The on-chip circuits act as an intermediary between the volatile controller memory and non-volatile storage, maintaining hot counts in non-volatile memory within the memory device itself. This intermediary approach ensures persistence without requiring the controller to maintain volatile state.
3Measurement precision
If the controller frequently updates and communicates hot count data, then accurate wear leveling is maintained, but communication overhead increases and performance decreases
Solution Approach 1:
The wear leveling management function is segmented into independent on-chip circuits that operate autonomously within the memory device. These circuits locally track hot counts and perform remapping operations without requiring frequent communication with the controller, reducing communication overhead while maintaining accuracy through on-chip verification.
Data Source
AI summary
A hot count records the number of erase operations experienced by a block. The hot count is stored in an overhead data area of the block and is updated by circuits located on the same substrate as the block. Where a memory has two or more planes, each plane has circuits for updating hot counts.