On-Chip IC Serial Identifier via Programmable Interconnect
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Solution Overview
Problem
Conventional methods for identifying Integrated Circuits (ICs) are visually based and fail to maintain traceability, especially when dies are coated or packaged, making it difficult and costly to track ICs back to their original position on a wafer.
Innovation Solution
An electrically measurable on-chip IC identifier is implemented using a programmable interconnect pattern within the IC, allowing for unique identification through direct probing, which can be integrated during wafer production without significant additional cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If visual inspection methods (microscope, X-rays) are used to identify ICs, then the identification process is simple and low-cost, but traceability is lost when dies are coated with opaque material or packaged
Solution Approach 1:
The patent replaces visual/optical identification methods with electrical measurement methods. Instead of using microscopes or X-rays to read visual patterns, the system uses electrical probes to measure resistance values of interconnect structures, thereby substituting optical detection with electrical detection to achieve identification through packaged devices
Solution Approach 2:
The identification pattern is nested within the interconnect structure itself. The visual ID pattern and electrical ID pattern share the same physical structure - the interconnect layers contain both visual patterns (for optical inspection) and electrical pathways (for electrical measurement), allowing dual-purpose identification without adding separate structures
2Reliability
If high volume pick and place and marking process is implemented at assembly level, then die identifiers can be reprinted on packages, but the process is extremely difficult and costly
Solution Approach 1:
The identification pattern is created during the wafer fabrication process itself, before packaging. The interconnect structure is designed to contain both visual and electrical ID patterns as part of the standard manufacturing process, eliminating the need for subsequent marking or printing operations at the assembly level
Solution Approach 2:
The interconnect structure serves multiple functions: it provides electrical connectivity for the circuit operation and simultaneously embeds the identification pattern for traceability. This multi-functionality eliminates the need for separate identification structures or post-fabrication marking processes
3Reliability
If an electrically measurable on-chip identifier is implemented, then full traceability is achieved, but the device cost may increase
Solution Approach 1:
The electrical identification pattern is merged with the standard interconnect structure of the IC. The same metal layers and vias that provide electrical connectivity are configured to form the ID pattern, combining the circuit functionality with the identification function without requiring additional material layers or separate fabrication steps
Data Source
AI summary
An apparatus comprising an integrated circuit, an interconnect layer within said integrated circuit, and one or more connections. The integrated circuit may be configured to provide an electrically measurable interconnect pattern by enabling one or more of a plurality of components. The one or more connections may each configured to enable a respective one of the components. The connections may be programmable while the apparatus is part of a wafer. The interconnect pattern may be configured to identify the apparatus after the apparatus has been manufactured.