On-Chip Clock Jitter Measurement Using Multi-Tap Delay Lines
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Solution Overview
Problem
Current on-chip jitter and duty cycle measurement techniques for high-speed clocks are limited by the need for special high-speed IOs, expensive equipment, and calibration requirements, making them unsuitable for high-frequency clocks and inefficient in terms of test throughput.
Innovation Solution
A system that measures the time interval between selected edges of a clock signal using an edge generator, multi-tap delay modules, and a multi-element phase detector, allowing for incremental delays and accurate jitter and duty cycle measurement without a reference clock or separate calibration, enabling measurement of high-frequency clocks and duty cycles with improved accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If off-chip measurement using oscilloscope and probe needle is used, then jitter characterization can be performed, but the probe needle capacitance and IO add extra jitter and limit maximum clock frequency
Solution Approach 1:
The invention extracts the measurement function from off-chip equipment (oscilloscope, probe needle) and implements it directly on-chip using digital circuits. The on-chip jitter measurement apparatus captures clock signal characteristics internally, eliminating the harmful effects of external probe needle capacitance and IO on measurement accuracy.
Solution Approach 2:
The invention introduces digital intermediaries (buffers, delay elements, logic circuits) between the clock signal source and measurement point. These digital intermediaries allow the measurement to be performed without direct external probing, avoiding the capacitance and jitter introduced by probe needles and external IO interfaces.
2Speed
If divided clock is used for measurement, then clock frequency can be reduced for measurement, but high-frequency jitter components are removed
Solution Approach 1:
The invention performs preliminary action by capturing multiple clock cycles and accumulating phase information before final jitter calculation. The phase detector accumulates phase differences over multiple cycles, allowing high-frequency jitter components to be preserved and accurately measured even when using lower measurement frequencies.
Solution Approach 2:
The invention uses periodic action by measuring phase differences over multiple clock cycles and accumulating the results. The jitter measurement is performed periodically across many cycles, allowing high-frequency components to be captured through the accumulation process rather than requiring single-cycle high-frequency measurement.
3Measurement precision
If programmable delay based technique is used, then cumulative distribution function can be obtained, but resolution is limited to one buffer delay making it unsuitable for high frequency clocks
Solution Approach 1:
The invention segments the delay measurement into multiple fine-grained delay elements arranged in series. Instead of using a single programmable delay element with coarse resolution, the phase detector uses multiple segmented delay stages, each contributing a small portion to the total measurable phase difference, thereby achieving fine resolution suitable for high-frequency clocks.
Solution Approach 2:
The invention transitions from a single-dimension delay measurement (one buffer delay) to a multi-dimensional approach by using multiple delay elements in series and accumulating phase information over multiple clock cycles. This dimensional expansion in the measurement space enables resolution much finer than a single buffer delay while maintaining high-frequency capability.
4Measurement precision
If Vernier delay line based technique is used, then sampling resolution finer than buffer delay can be obtained, but it can only work for low-frequency clocks and high-frequency jitter components are eliminated
Solution Approach 1:
The invention creates a universal measurement apparatus that can handle both low and high-frequency clocks without requiring different measurement techniques. The on-chip phase detector and delay elements are designed to provide fine sampling resolution that works across a broad frequency range, eliminating the need to switch between different measurement methodologies for different frequency bands.
Solution Approach 2:
The invention changes the parameters of the delay elements and phase detector to optimize for high-frequency operation while maintaining fine resolution. By adjusting the delay element characteristics and using digital accumulation techniques, the system achieves sampling resolution finer than a single buffer delay while remaining functional at high clock frequencies where traditional Vernier delay lines fail.
5Productivity
If on-chip measurement is implemented, then high test throughput can be achieved without special high-speed IOs and expensive equipment, but measurement accuracy must be maintained
Solution Approach 1:
The invention implements self-service by using the chip's own digital logic resources (buffers, delay elements, logic circuits) to perform the measurement function. The on-chip apparatus uses the chip's internal signal distribution network and existing digital infrastructure to capture and measure jitter, eliminating the need for external expensive equipment while maintaining measurement accuracy through careful digital circuit design.
Data Source
AI summary
An apparatus for measuring time interval between two selected edges of a clock signal. includes an edge generator, a first multi-tap delay module, a second multi-tap delay module, and a multi-element phase detector. The edge generator produces a first edge at a first output node and a second selected edge at a second output node. First multi-tap delay module provides a first constant incremental delay at each tap to the first edge. Second multi-tap delay module provides a second constant incremental delay at each tap to the second selected edge. Each element of the multi-element phase detector has a first input terminal and a second input terminal. The first input terminal is coupled to a selected tap of the first multi-tap delay module and the second input terminal is coupled to a corresponding tap of the second multi-tap delay module. The output terminals of the multi-element phase detector provide the value of the time interval.