On-Chip Jitter Injection Using Variable Delay for Loop-Back I/O Test
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Solution Overview
Problem
Current testing methods for high-speed serial I/Os lack the capability to effectively measure and control jitter, leading to prolonged test times and potential false rejection of functioning devices, due to the inability to accurately assess deterministic and random jitter within high-speed interfaces like PCI Express and USB 2.0.
Innovation Solution
An on-chip jitter injection system using a variable delay mechanism, integrated into a loop-back test circuit, allows for controlled injection and measurement of jitter, enabling the determination of multiple points on the bathtub curve and separation of deterministic and random jitter components, thereby improving fault detection and reducing test time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If off-chip jitter injection is used on loadboard or ATE, then jitter can be injected into high-speed signals, but it requires expensive specialized ATE cards and increases tester costs
Solution Approach 1:
The patent merges the jitter injection function directly into the on-chip transceiver circuitry by integrating a variable delay line with the clock-data recovery (CDR) circuit. This eliminates the need for separate off-chip jitter injection equipment, thereby reducing tester costs while maintaining the capability to inject controlled jitter for testing purposes.
Solution Approach 2:
The transceiver circuit is designed to perform self-testing by generating and injecting its own jitter signals through the integrated variable delay line. This self-service capability allows the device to test its own jitter tolerance without requiring external specialized equipment, reducing dependency on expensive ATE cards.
2Reliability
If off-chip jitter injection is used, then jitter can be injected into high-speed signals, but it requires high-speed signals to be routed on the loadboard
Solution Approach 1:
The jitter injection function is merged into the on-chip circuitry, eliminating the need for loadboard routing of high-speed signals for jitter injection. The variable delay line is integrated within the transceiver, allowing jitter to be injected internally without requiring complex loadboard configurations.
3Ease of manufacture
If normal loop-back test is used, then transmitter and receiver can be tested, but the CDR will not be tested for jitter tolerance because the Tx sends a clean signal
Solution Approach 1:
The variable delay line is placed in the signal path before the CDR circuit to pre-modulate the signal with jitter. This preliminary action ensures that the CDR circuit receives a jittered signal during loop-back testing, enabling proper testing of jitter tolerance without requiring separate test equipment.
4Measurement precision
If BER measurement is performed to verify bit-error rate, then device functionality can be verified, but measurement time becomes very long (hours or days) to achieve BER of 10^-12
Solution Approach 1:
The variable delay line pre-modulates the test signal with controlled jitter before it reaches the CDR circuit. By introducing known amounts of jitter in advance, the test can accelerate the accumulation of bit errors, allowing BER measurement to reach 10^-12 much faster without compromising measurement precision.
Solution Approach 2:
The variable delay line dynamically adjusts the jitter amount to optimize test conditions. By varying the delay to create different jitter scenarios, the system can accelerate error generation while maintaining accurate BER measurement, significantly reducing test time compared to static testing methods.
5Ease of manufacture
If fixed delay is used in jitter injection, then simple implementation is achieved, but well-defined and controllable jitter cannot be generated
Solution Approach 1:
The patent implements a variable delay line that can dynamically adjust its delay value, enabling precise control of jitter amplitude. This dynamic structure allows the system to generate well-defined and controllable jitter while maintaining relative implementation simplicity through standard circuit design techniques.
Solution Approach 2:
The variable delay line changes its delay parameter to create controlled jitter. By adjusting the delay value, the system can generate different amounts of jitter in a controlled manner, achieving both manufacturing precision and implementation feasibility.
Data Source
AI summary
High Speed I/O interfaces (600) such as DVI, S-ATA or PCI-Express require expensive test equipment. Loop-back tests are widely used as one alternative, but lack coverage of timing-related defects. A system and method for on-chip jitter injection using a variable delay (203) with controllable amplitude (501) and high accuracy is provided that improves the coverage of loop-back tests.