On-Chip Junction Capacitor for Power Management IC
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Solution Overview
Problem
High-frequency power conversion applications face limitations due to switching node ringing voltage, which is difficult to suppress effectively without compromising device performance or increasing costs, especially in high-speed power devices like MOSFETs.
Innovation Solution
Integration of a junction capacitor on-chip with a power management IC device, utilizing a buried layer and epitaxial layer to form a P/N junction capacitor, which reduces switching node ringing voltage and enhances capacitance density without increasing device area or cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high-speed power devices are used to increase switching frequency, then power density and system efficiency are improved, but switching node ringing voltage increases due to reverse recovery charge
Solution Approach 1:
The patent utilizes the reverse recovery charge that causes ringing voltage harm and converts it into a useful charging current for an integrated capacitor. The capacitor is specifically designed to charge during the reverse recovery period of the low-side MOSFET, transforming the harmful ringing energy into beneficial stored energy that suppresses subsequent voltage spikes and improves overall system efficiency.
2Object-generated harmful factors
If conventional capacitors are used to suppress ringing voltage, then switching node voltage stability is improved, but device area and cost increase
Solution Approach 1:
The patent merges the capacitor with the power device structure by integrating it into the substrate. The capacitor shares the same substrate and utilizes the same fabrication processes as the power device, eliminating the need for separate capacitor components and reducing overall device area while maintaining effective ringing voltage suppression.
Solution Approach 2:
The integrated capacitor serves multiple functions: it suppresses ringing voltage, stores energy during reverse recovery, and can be fabricated using the same processes as the power device. This multi-functionality reduces the need for additional components and simplifies the overall device structure.
3Object-generated harmful factors
If p-type body doping concentration is reduced to decrease Qrr, then reverse recovery charge is reduced, but threshold voltage decreases allowing more current during dead time which triggers parasitic bipolar transistor
Solution Approach 1:
The patent segments the doping structure by introducing a localized N-type buried layer beneath the P-type body. This segmentation allows the P-type body doping to be optimized for lower Qrr while the N-type buried layer provides a depletion region that prevents parasitic bipolar transistor triggering, effectively decoupling the two conflicting requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively suppresses switching node ringing voltage, expands the frequency range of device operation, and improves power efficiency while maintaining a smaller form factor compared to traditional capacitor schemes.
Implementation Method 1
The epitaxial layer and the buried layer, together, form a junction capacitor
Data Source
AI summary
A power semiconductor device includes a substrate of a first conductivity type, a buried layer of a second conductivity type formed in at least a portion of the substrate, and at least one epitaxial layer of the first conductivity type formed on at least a portion of an upper surface of the substrate and covering the buried layer. The epitaxial layer and the buried layer form a junction capacitor. The device further includes at least one active power transistor formed in an upper surface of the epitaxial layer and above at least a portion of the buried layer.