On-Chip Protocol Analyzer for SerDes Link Integrity

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Solution Overview

Problem

Existing external link analyzers can affect signal integrity and data integrity during communication link negotiations, and they often require significant storage capacity and may not be physically feasible to implement in all scenarios.

Innovation Solution

The implementation of on-chip link analysis and an on-chip protocol analyzer that performs real-time filtering and data compression, allowing for reduced storage needs and minimizing the impact on link characteristics.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Difficulty of detecting and measuring

If an external link analyzer is used to capture negotiation packets, then link analysis capability is improved, but signal integrity and data integrity deteriorate

Engineering Contradiction:

Improvelink analysis capabilityVSAvoidsignal integrity and data integrity

Core Design Contradiction:

Difficulty of detecting and measuringVSReliability

Solution Approach 1:

The patent extracts the link analysis functionality from an external device and integrates it directly into the SerDes circuitry. The tap circuitry is embedded within the SerDes to capture negotiation packets internally, eliminating the need for external analyzers that would interfere with signal integrity while maintaining full link analysis capability.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The link analyzer functionality is nested within the SerDes structure itself. The tap circuitry, compression logic, and trace memory are all integrated as internal components of the SerDes, allowing the system to monitor and analyze its own communication signals without external intervention that could degrade signal quality.

Inventive Principle:

Principle #7Nested doll (Nesting)

2Loss of information

If an external link analyzer with full storage capacity is used, then complete negotiation packet capture is improved, but device size and storage requirements worsen

Engineering Contradiction:

Improvenegotiation packet capture completenessVSAvoidstorage device size

Core Design Contradiction:

Loss of informationVSVolume of stationary object

Solution Approach 1:

The patent applies data compression algorithms that transform the stored negotiation packet data into a more compact form. By changing the parameter representation of captured packets through compression, the system maintains complete information capture capability while significantly reducing the storage volume required in the trace memory.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The system captures all negotiation packets (excessive action) but then applies compression to reduce the stored volume. This approach ensures no information is lost during capture while the compression step efficiently reduces the final storage requirements, achieving both complete capture and compact storage.

Inventive Principle:

Principle #16Partial or excessive action

3Difficulty of detecting and measuring

If external link analyzers are implemented, then link debugging capability is improved, but physical feasibility worsens in certain scenarios

Engineering Contradiction:

Improvelink debugging capabilityVSAvoidphysical feasibility

Core Design Contradiction:

Difficulty of detecting and measuringVSEase of manufacture

Solution Approach 1:

The patent merges the link debugging functionality with the existing SerDes manufacturing process. By integrating the tap circuitry, compression logic, and trace memory directly into the SerDes chip, the system achieves full link debugging capability as part of the standard device fabrication, eliminating the need for separate external analyzer hardware and improving physical feasibility.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS12309242B2On-chip link analysis

Publication Date: 2025.05.20 MICROSEMI SOLUTIONS US INC

AI summary

One or more examples relate to an on-chip protocol analyzer provided at a physical layer of a communication interface to receive information about link control process data carried by a communication system to or from a protocol control logic of the communication interface.