On-Chip Lock for Parallel Memory Data Bus Access
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Solution Overview
Problem
The existing integrated circuits experience slowed data communication speed between on-chip memory and peripheral devices due to the time-consuming process of assessing access rights and controlling memory access.
Innovation Solution
An on-chip lock is introduced to block access to the memory data bus until access rights are granted, allowing the memory to set logical values in parallel with the access rights assessment, thereby reducing the time required to access data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the access right manager assesses access rights before granting access to the memory segment, then the security and access control are ensured, but the data communication speed between the on-chip memory and the peripheral device is slowed down
Solution Approach 1:
The patent applies preliminary action by allowing the on-chip memory to set logical values on the memory data bus wires in advance, before the access right manager completes its assessment. The lock mechanism enables this preliminary action to occur safely by blocking the bus during the assessment period, so that when access is granted, the data is already prepared and ready for immediate transmission, thus maintaining security while improving communication speed
2Reliability
If the on-chip memory is controlled to set logical values on the memory data bus wires only after access rights are granted, then the access control security is maintained, but the time required to access data is increased
Solution Approach 1:
The lock mechanism enables preliminary action by allowing the memory to prepare data (set logical values) on the memory data bus before access rights are finally granted. This preparation occurs in parallel with the access right assessment, so that when the lock is released and access is granted, the data is already in place, significantly reducing the actual memory access time while maintaining security through the locked state during assessment
3Productivity
If the lock blocks access to the memory data bus during the access rights assessment, then the data communication speed is improved by enabling parallel processing, but the device complexity increases due to the additional lock component
Solution Approach 1:
The lock acts as an intermediary component between the access right manager and the memory data bus. It mediates the conflict between security requirements and speed requirements by providing a controlled blocking mechanism that enables parallel processing of data preparation and access assessment, thus improving productivity while adding only a single, relatively simple circuit element to the overall system
Data Source
AI summary
An integrated circuit having an on-chip access right manager to grant or deny access to a memory segment to a peripheral device such as a CPU (Central Processing Unit), DSP (Digital Signal Processor) or DMA (Direct Memory Access) unit according to predetermined access rights upon reception of a read instruction from the peripheral device, and an on-chip lock connected to a memory data bus, the lock being controllable by the access right manager to block access to a logical one or zero set on each memory data bus wires as long as the access to the memory segment is not granted. Upon reception of the read instruction from the peripheral device, the integrated circuit is configured to start both the process of setting, by the on chip memory, of either a logical one or a logical zero on each of the wires of the memo data bus, as well as the process of granting or refusing the access to the memory segment by the on-chip access right manager to the peripheral device.