On-Chip Memory Bank Architecture for Concurrent Low-Latency Access
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Solution Overview
Problem
Integrated circuits (ICs) face challenges in providing a high-bandwidth, low-latency memory access mechanism that can be concurrently accessed by multiple subsystems, leading to inefficiencies in processing operations such as those required for Computational Neural Networks (CNNs).
Innovation Solution
An on-chip memory block circuit with multiple interfaces and independently controllable memory banks, directly connected to both processing systems and programmable logic, allowing concurrent access and reducing the need for external RAM, thereby enhancing data storage and retrieval efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If external RAM is used for data storage, then storage capacity is sufficient, but access latency increases and bandwidth is reduced
Solution Approach 1:
The memory system is segmented into multiple independent memory banks (Bank 0, Bank 1, Bank 2, Bank 3) that can be accessed simultaneously by different interfaces. This segmentation allows parallel access operations, increasing effective bandwidth and reducing access latency without requiring a single large external memory component.
Solution Approach 2:
The patent transitions from a single shared memory resource to a multi-dimensional memory architecture with multiple banks and multiple interfaces. This dimensional expansion allows concurrent access from multiple subsystems (programmable logic, processor system, IP blocks) simultaneously, effectively increasing access speed and bandwidth.
2Productivity
If multiple subsystems access shared memory concurrently, then resource utilization improves, but access conflicts and latency increase
Solution Approach 1:
By dividing the memory into separate banks, the patent eliminates access conflicts between subsystems. Each interface can access different banks simultaneously without contention, maintaining high resource utilization while preventing latency increases that would result from shared access arbitration.
Solution Approach 2:
The switch fabric acts as an intermediary that routes access requests from multiple interfaces to appropriate memory banks. This mediation enables concurrent access operations while managing resource allocation, ensuring high productivity without incurring arbitration delays.
3Loss of time
If on-chip memory banks are implemented, then access latency is reduced, but chip area increases
Solution Approach 1:
The memory is divided into multiple smaller banks rather than implementing one large on-chip memory. This segmentation reduces the area impact of on-chip memory while maintaining low latency benefits, as each bank can be optimized for speed and the distributed architecture enables parallel access operations.
Solution Approach 2:
The memory block circuit with multiple banks and interfaces serves multiple functions: it provides fast on-chip storage, enables concurrent access by multiple subsystems, and can be configured to serve different applications (CNN processing, general-purpose computing). This multi-functionality justifies the chip area investment by delivering both speed and versatility.
Data Source
AI summary
A memory block circuit can include a plurality of data interfaces, a switch connected to each data interface of the plurality of data interfaces, and a plurality of memory banks each coupled to the switch. Each memory bank can include a memory controller and a random access memory connected to the memory controller. The memory block circuit also includes a control interface and a management controller connected to the control interface and each memory bank of the plurality of memory banks. Each memory bank can be independently controlled by the management controller.