On-Chip Memory Latency Control for AP-CP Integration
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Solution Overview
Problem
In mobile devices, the integration of an Application Processor (AP) and a Communication Processor (CP) on a single chip leads to increased memory latency, particularly in DRAM access, which hinders real-time processing and communication performance, making it difficult to maintain stable communication and display functions.
Innovation Solution
An on-chip memory system that monitors memory traffic for multiple Intellectual Properties (IPs) and dynamically controls storage usage, incorporating a cache or buffer to manage memory latency, ensuring fixed latency conditions for real-time IP processes and improving communication bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If AP and CP are integrated on one chip, then device miniaturization is achieved, but memory latency increases
Solution Approach 1:
The patent divides the memory system into multiple independent memory banks (first memory bank for AP, second memory bank for CP) within the integrated chip. This segmentation allows each processor to access its dedicated memory bank without interference from the other processor's memory accesses, thereby reducing memory latency while maintaining the miniaturization benefits of integration.
Solution Approach 2:
The patent introduces a memory controller as an intermediary component that manages memory access between the AP, CP, and the memory banks. The memory controller prioritizes CP memory requests when both processors access memory simultaneously, acting as a mediator that resolves access conflicts and ensures low latency for real-time communication processing.
2Loss of time
If priority based QoS is applied to secure latency for real-time IP, then real-time process latency is reduced, but throughput of low priority transactions decreases
Solution Approach 1:
The patent segments the memory access path by providing separate memory banks for AP and CP, with dedicated memory controllers for each. This segmentation allows independent optimization: the CP memory controller can prioritize real-time communication traffic to ensure low latency, while the AP memory controller manages general data throughput without interfering with CP's real-time requirements, thus resolving the throughput-latency tradeoff.
Solution Approach 2:
The patent applies different quality characteristics to different memory access paths. The CP memory bank is optimized for low latency with priority-based QoS for real-time communication, while the AP memory bank is optimized for general throughput. This local optimization allows each processor to have tailored memory performance characteristics suited to their specific workloads.
3Productivity
If TCM and cache are used in CP to reduce memory latency, then CP processing speed is improved, but device complexity increases
Solution Approach 1:
The patent merges the TCM and cache structures into a unified memory bank architecture for the CP. Instead of implementing separate TCM and cache subsystems with independent control logic, the patent integrates these functions into a single memory bank that provides both high-speed storage and caching capabilities, thereby reducing overall system complexity while maintaining the performance benefits.
Solution Approach 2:
The memory bank designed for the CP serves multiple functions simultaneously: it acts as TCM for critical real-time data, provides cache for frequently accessed code and data, and supports DMA transfers. This multi-functionality eliminates the need for separate dedicated hardware blocks for each function, reducing device complexity while improving CP processing speed.
Data Source
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AI summary
An electronic device, an on-chip memory and a method of operating the on-chip memory are disclosed. The on-chip memory including an on-chip memory comprises: a plurality of design Intellectual Property (IPs), a memory that includes a storage area and a processor connected to the memory, wherein the processor is configured to monitor a memory traffic of at least one IP among the plurality of design IPs, and control usage of a storage area based on a result of the monitoring. According to the electronic device, the on-chip memory and the method of operating the on-chip memory of the present disclosure, in an AP-CP one chip structure, a stable communication is secured, memory latency is secured for a code required to process a real time of a CP, and in the AP-CP one chip structure, a communication bandwidth is improved.