Programmable On-Chip Network for Energy-Minimal CGRA Dataflow
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Solution Overview
Problem
Existing programmable cores are inefficient, wasting up to 90% of their energy on overheads, and prior CGRAs struggle to support complex control flow and irregular computations, leading to energy inefficiencies and long compilation times.
Innovation Solution
A novel co-designed CGRA compiler and architecture that supports arbitrary control flow and memory access patterns without expensive hardware mechanisms, using a steering control paradigm and new control-flow primitives, and a compiler that optimizes and maps high-level code to the CGRA fabric efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional programmable cores are used, then generality is achieved, but energy efficiency deteriorates (spending 90-95% energy on overheads)
Solution Approach 1:
The system segments computation into a coarse-grained array of processing elements (PEs) connected by an on-chip network, separating computation from control and enabling independent optimization of each segment for energy efficiency while maintaining overall programmability
Solution Approach 2:
The patent replaces traditional von Neumann architecture mechanisms (instruction fetch/control, centralized register file) with a dataflow-based system where computations are mapped directly onto the PE array and executed through data movement along predetermined paths, eliminating overhead mechanisms
2Use of energy by moving object
If prior CGRAs support simple control flow, then energy efficiency is improved, but support for complex programming idioms deteriorates
Solution Approach 1:
The system provides dynamic reconfiguration capabilities where the CGRA can be programmatically adapted to support complex control flow patterns through runtime configuration of the on-chip network routing and PE activation, enabling the same hardware to efficiently execute both simple and complex programs
Solution Approach 2:
The CGRA architecture is designed with universal capabilities to accommodate diverse computation patterns and control flow structures through a single unified platform, using software-defined routing and configuration mechanisms to handle various programming idioms without requiring specialized hardware for each pattern
3Adaptability or versatility
If prior CGRAs use expensive hardware mechanisms for control flow, then support for complex control flow is improved, but energy consumption increases
Solution Approach 1:
The system leverages the existing on-chip network infrastructure to provide control flow functionality, where routing decisions and data movement are handled by the network itself rather than requiring separate expensive control mechanisms, allowing the same hardware to serve both data communication and control purposes
4Use of energy by moving object
If compiler optimizes for CGRA mapping, then energy efficiency is improved, but compilation time increases
Solution Approach 1:
The compiler performs preliminary optimization and mapping decisions during the compilation process, pre-computing efficient dataflow graphs and PE assignments that can be directly implemented on the CGRA without requiring time-consuming runtime optimization, thereby reducing overall system time while maintaining energy efficiency
Data Source
AI summary
Disclosed herein is a co-designed compiler and CGRA architecture that achieves both high programmability and extreme energy efficiency. The architecture includes a rich set of control-flow operators that support arbitrary control flow and memory access on the CGRA fabric. The architecture is able to realize both energy and area savings over prior art implementations by offloading most control operations into a programmable on-chip network where they can re-use existing network switches.