On-Chip Network Interface for AMBA Bus Bandwidth Bottlenecks
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Solution Overview
Problem
The AMBA 2.0 on-chip bus protocol experiences bandwidth limitations and communication bottlenecks due to physical sharing of wires, causing master modules to wait for grants to use the bus, especially when multiple master modules request access to different slave modules simultaneously.
Innovation Solution
An on-chip network interfacing apparatus with a switch and interface units that enable simultaneous communication among modules by transmitting data in packet units, allowing multiple master modules to communicate without waiting for bus grants, using a switch that decodes tags in packets to direct them to their destinations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the AMBA 2.0 on-chip bus protocol is used to establish communications between on-chip circuits, then the structure is simple and easy to implement, but the bandwidth is limited due to physical sharing of wires causing master modules to wait for bus grants
Solution Approach 1:
The patent segments the communication system into multiple independent communication channels or paths within the on-chip network, allowing multiple master modules to simultaneously transmit data packets through different paths to different slave modules, thereby eliminating the need for sequential bus grants and increasing overall communication bandwidth
Solution Approach 2:
The patent introduces an on-chip network interface as an intermediary layer between the AMBA bus and the target modules. This interface translates AMBA bus transactions into packet-based network communications, enabling concurrent access multiple modules without contending for the same physical bus resources, thus resolving the bandwidth limitation
2Productivity
If multiple master modules simultaneously request access to different slave modules, then communication parallelism is needed, but the physical bus sharing causes communication bottlenecks
Solution Approach 1:
The patent transitions from a one-dimensional sequential bus architecture to a multi-dimensional packet-switched network architecture where multiple data flows can coexist in different spatial and temporal dimensions. This allows simultaneous communications between multiple master-slave pairs by routing packets through different network paths, effectively adding dimensional capacity to the communication system
3Productivity
If packet-based communication is used to allow simultaneous communication, then communication efficiency improves, but the interface complexity between AMBA bus and on-chip network increases
Solution Approach 1:
The patent designs the on-chip network interface with multi-functional capabilities that handle multiple AMBA bus protocols (such as AHB, APB, OPB) and packet formats through a unified architecture. This universal interface can simultaneously support different types of master and slave modules, reducing the need for multiple specialized interfaces and thereby limiting the increase in overall system complexity
Data Source
AI summary
An on-chip network interfacing apparatus and method are provided. The apparatus includes a plurality of on-chip network ports; a switch receiving data from a first on-chip network port of the on-chip network ports and transmitting the received data to a second on-chip network port of the on-chip network ports; and an interface unit interfacing an advanced microcontroller bus architecture (AMBA) signal received from an module, which is designed according to an AMBA on-chip bus protocol, and outputting the interfacing result to the first on-chip network port; and interfacing the on-chip network signal received from the first on-chip network port, and outputting the interfacing result to the module. Accordingly, it is possible to establish communications at increased speeds by interfacing a signal according to the AMBA 2.0 on-chip bus protocol with a signal according to the on-chip network protocol.