On-Chip Network Multiplexer Architecture for Multi-Core Task Communication

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Solution Overview

Problem

Existing computing systems with multiple processing cores face challenges in efficiently updating and communicating processing tasks across cores, leading to suboptimal performance and resource utilization under varying loads, particularly in dynamic multi-core environments.

Innovation Solution

A hardware-based on-chip network architecture that enables non-blocking task switching and inter-task communication by using multiplexers to connect cores to task-specific memory segments, allowing tasks to run on any core without needing cross-connectivity, thus optimizing resource allocation and minimizing overhead.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If traditional cross-connectivity architecture is used for inter-task communication, then tasks can communicate between any cores, but system complexity and wiring overhead increase significantly

Engineering Contradiction:

Improveinter-task communication capabilityVSAvoidwiring and logic overhead

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent introduces task-specific memory segments as intermediaries for inter-task communication. Instead of direct core-to-core connectivity, tasks write data to another task's memory segment through multiplexers, which act as mediators. This eliminates the need for complex cross-connect wiring between cores while maintaining full communication capability.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The multiplexer network provides universal access to all task memory segments from any core. The same multiplexer infrastructure used for memory image transfers is also used for inter-task communication, eliminating the need for separate communication wiring and reducing overall system complexity.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If system software is used for task switching and memory image transfers, then dynamic allocation can be managed, but processing time is lost due to software overhead

Engineering Contradiction:

Improvedynamic task allocationVSAvoidsoftware overhead time

Core Design Contradiction:

Adaptability or versatilityVSLoss of time

Solution Approach 1:

The hardware automatically manages task switching and memory image transfers without software intervention. The multiplexer network and controller handle context switching, memory image transfer, and task allocation autonomously through hardware logic, eliminating software overhead and enabling continuous processing without time loss.

Inventive Principle:

Principle #25Self-service

Solution Approach 2:

The patent replaces software-based task management with hardware-based automation. The controller and multiplexer network use hardware logic to perform task switching and memory management functions that would traditionally require software execution, thereby eliminating the time overhead associated with software interpretation and execution.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

3Adaptability or versatility

If cores hold multiple task images in memory, then task switching is enabled, but memory usage and complexity increase

Engineering Contradiction:

Improvetask switching capabilityVSAvoidmemory resources per core

Core Design Contradiction:

Adaptability or versatilityVSQuantity of substance

Solution Approach 1:

The patent divides the memory system into task-specific memory segments, with each segment dedicated to a specific task. Instead of each core holding multiple task images, each task has its own memory segment in the shared memory system, accessible through multiplexers. This segmentation reduces memory requirements per core while enabling task switching.

Inventive Principle:

Principle #1Segmentation

4Productivity

If the number of cores and applications increases, then processing capacity grows, but network and memory architecture scalability becomes challenging

Engineering Contradiction:

Improveprocessing throughputVSAvoidnetwork architecture complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent implements a scalable multiplexer architecture where the same partial infrastructure serves multiple purposes. The multiplexer network is designed to handle both memory image transfers and inter-task communication, and can be expanded by adding more multiplexer stages rather than redesigning the entire system, enabling scalable growth with controlled complexity.

Inventive Principle:

Principle #16Partial or excessive action

Data Source

PatentUS8930958B2Efficient network and memory architecture for multi-core data processing

Publication Date: 2015.01.06 THROUGHPUTER INC

AI summary

The invention provides hardware logic based techniques for a set of processing tasks of a software program to efficiently communicate with each other while running in parallel on an array of processing cores of a multi-core data processing system dynamically shared among a group of software programs. These inter-task communication techniques comprise, by one or more task of the set, writing their inter-task communication information to a memory segment of other tasks of the set at the system memories, as well as reading inter-task communication information from their own segments at the system memories. The invention facilitates efficient inter-task communication on a multi-core fabric, without any of the communications tasks needing to know whether and at which core in the fabric any other task is executing at any given time. The invention thus enables flexibly and efficiently running any task of any program at any core of the fabric.