On-Chip Network Reorder Buffer Segmentation for Deadlock Prevention
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Solution Overview
Problem
In a System-on-a-Chip (SoC), the limited space and power constraints pose challenges in maintaining proper ordering of transaction responses across multiple initiator and target IP cores, particularly when dealing with concurrent transactions and varying performance rates, leading to potential deadlocks and inefficiencies in the interconnect network.
Innovation Solution
The implementation of optimally distributed reorder storage buffers across initiator and target agents, configured by selectable parameters, allows for concurrent transaction processing and reordering of responses without violating response ordering dependencies, ensuring efficient transmission and avoiding deadlocks by allowing more responses to be pending than can be stored, thus maintaining proper sequential ordering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If reorder storage buffers are implemented to maintain response ordering, then response ordering dependencies are satisfied, but chip space consumption increases
Solution Approach 1:
The reorder buffer is segmented into multiple independent buffers, each associated with a specific initiator port. This segmentation allows the system to maintain ordering for individual initiators without requiring a single large buffer that would consume excessive chip space. Each buffer only stores responses for its associated initiator, reducing overall memory requirements while maintaining ordering guarantees.
Solution Approach 2:
The patent implements local reorder buffers at each initiator port rather than a centralized buffer. This local quality approach allows each initiator to have its own ordering management, reducing the total space needed since not all initiators simultaneously require buffering. The local buffers are sized according to specific initiator needs rather than provisioning for worst-case system-wide scenarios.
2Reliability
If reorder storage buffers are implemented to prevent deadlocks, then system reliability improves, but power consumption increases
Solution Approach 1:
The flow logic dynamically manages buffer allocation and transaction routing based on real-time system state. Instead of static buffering approaches that consume power continuously, the system adaptively allocates buffer space and routes transactions through available paths, reducing power consumption by activating only the necessary components for current workload requirements while maintaining deadlock-free operation.
Solution Approach 2:
The patent introduces flow logic as an intermediary that coordinates between initiators and targets, managing buffer usage and transaction flow. This intermediary prevents deadlocks by orchestrating transaction completion and buffer release, eliminating the need for overly conservative buffering strategies that would consume excessive power. The flow logic acts as a mediator that enables efficient resource utilization while maintaining system reliability.
3Productivity
If transactions are routed to different target ports for concurrent processing, then throughput increases, but response ordering may be violated
Solution Approach 1:
The system segments the buffering function by initiator port, creating independent reorder buffers for each initiator. This segmentation allows concurrent transactions from the same initiator to be routed to different target ports for parallel processing, while each initiator's buffer independently manages its responses to maintain ordering. The segmentation enables throughput improvement through parallelism while preserving ordering guarantees through isolated buffer management.
Solution Approach 2:
The flow logic serves as an intermediary that routes transactions from initiators to multiple target ports while coordinating response delivery. It maintains a mapping between transactions and their expected order, allowing concurrent processing at different targets while ensuring responses are delivered in the correct sequence to each initiator. This intermediary coordination enables both high throughput through parallelism and reliable ordering through centralized flow management.
Data Source
AI summary
Flow logic supports concurrency of multiple threads and/or tag IDs to be concurrently communicated across the interconnect while allowing the one or more target IP cores to be able to reorder incoming request transactions from the initiator IP core in a manner that is optimal for that target IP core while relieving that target IP core from having to maintain the sequential issue order of transaction responses to the incoming request transactions in the thread or tags when processed by the target IP core. The flow logic cooperates with the reorder storage buffers to control an operation of the reorder storage buffers as well as control issuance of at least the request transactions from the initiator IP core onto the interconnect in order to maintain proper sequential ordering of the transaction responses for the thread or tags when the transaction responses are returned back to the initiator IP core.