On-Chip Noise Generator Circuit for Memory Power Bus Testing
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Solution Overview
Problem
Existing memory device testing techniques face challenges in accessing and accurately testing internal components, particularly power buses, due to their complexity and density, leading to inadequate results and prolonged time for component failure detection.
Innovation Solution
Incorporating on-chip device testing circuits that induce noise on power buses using a bus shorting circuit and noise generator circuit to simulate and exaggerate real-world conditions, allowing targeted testing and accelerated debugging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If in-shop testers are used to test memory devices, then testing can be performed externally, but the testers cannot accurately simulate real-world noise conditions on power buses
Solution Approach 1:
The patent introduces an on-chip noise generator circuit as an intermediary component that actively generates noise signals on power buses during testing. This mediator bridges the gap between clean external tester environments and noisy real-world conditions, enabling accurate simulation of power bus noise without requiring external testers to have complex noise simulation capabilities.
Solution Approach 2:
The memory device performs its own self-testing by incorporating on-chip test circuits that can autonomously generate noise on power buses and monitor component responses. This self-service approach eliminates the need for external testers to simulate noise conditions, allowing the device to test itself under realistic operating conditions.
2Productivity
If memory circuits are made more complex and dense, then functionality is improved, but access to internal components for testing becomes limited
Solution Approach 1:
The patent embeds test circuits and noise generators directly within the memory device architecture, nesting testing functionality inside the dense memory structure. This allows testing capabilities to be integrated at the component level without increasing external device size or complexity, maintaining memory density while enabling internal component access.
Solution Approach 2:
The patent shifts testing from an external dimensional approach to an internal on-chip dimension by integrating test circuits within the same silicon substrate. This dimensional transition allows testing of previously inaccessible internal components without requiring physical access to external interfaces.
3Ease of operation
If external testers are used for testing, then device access is simpler, but the time to detect component failures is prolonged
Solution Approach 1:
The patent implements preliminary testing actions by incorporating on-chip circuits that can immediately generate noise and detect failures during normal operation. This preliminary action allows failures to be detected in real-time rather than waiting for external testing schedules, significantly reducing failure detection time while maintaining operational simplicity.
Data Source
AI summary
An apparatus having a power bus supplying power to a component of a memory device. The apparatus includes a noise source circuit generating a plurality of noise source signals that simulate a real-world noise. The apparatus can include a pulse generator circuit that receives the noise source signal and outputs at least one noise profile signal based on the noise source signal. A bus shorting circuit can be connected to the pulse generator circuit to receive the at least one noise profile signal. The bus shorting circuit can have at least one transistor connected between a first rail and a second rail of the power bus. Based on the at least one noise profile signal, the bus shorting circuit intermittently connects the at least one transistor between the first rail to the second rail to induce noise on the power bus.