On-Chip Noise Detection Circuit for Low-Frequency IC Testing
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Solution Overview
Problem
Integrated circuit (IC) testing in platforms like Wafer Acceptance Test (WAT) is challenging due to equipment limitations, such as a restricted clock signal frequency of 10 MHz and the requirement for specific devices like a GSG probe card, which complicates the detection of noise levels.
Innovation Solution
A noise detecting system comprising an amplifier circuit, a filtering circuit, and a comparing circuit, integrated into an IC and formed on a semiconductor substrate, which amplifies, filters, and compares signals to determine noise levels, using a clock generator and analyze device to derive noise levels without exceeding the 10 MHz frequency constraint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional noise detection methods are used in WAT platform, then equipment limitations (10 MHz clock frequency constraint and GSG probe card requirement) prevent accurate noise measurement, but the patent integrates a noise detecting circuit directly into the IC to overcome these limitations
Solution Approach 1:
The noise detecting circuit is integrated directly into the IC device, merging the detection function with the tested circuit. This eliminates the need for external specialized equipment like GSG probe cards and high-frequency clock generators, while enabling accurate noise measurement within the 10 MHz constraint.
Solution Approach 2:
The IC device performs its own noise detection through the integrated noise detecting circuit, which includes an amplifier circuit, filtering circuit, and comparing circuit. The system uses itself as the measurement tool, eliminating dependency on external specialized equipment.
2Measurement precision
If the clock signal frequency is limited to 10 MHz in WAT platform, then high-frequency noise components cannot be detected, but the patent uses a filtering circuit with cutoff frequency above 10 MHz to capture relevant noise
Solution Approach 1:
The filtering circuit is designed with a cutoff frequency parameter set above 10 MHz, allowing it to pass noise components in the detectable frequency range while blocking higher frequencies. This parameter optimization enables accurate noise measurement within the system's frequency constraints.
3Ease of operation
If specialized GSG probe cards are required for testing, then the testing process becomes more complex and less accessible, but the patent enables standard probe card compatibility through integrated circuit design
Solution Approach 1:
The noise detecting circuit is designed with universal interfaces that are compatible with standard probe cards, eliminating the need for specialized GSG probe cards. The integrated design provides multiple functions (noise detection, signal amplification, filtering, and comparison) through a single circuit block that can be accessed by conventional testing equipment.
Data Source
AI summary
A noise detecting circuit including an amplifier circuit, a filtering circuit and a comparing circuit. The amplifier circuit is arranged to amplify an input signal and output an amplified signal, wherein the input signal is received from a circuit to be detected and indicates a noise level of the circuit to be detected. The filtering circuit is coupled to the amplifier circuit and arranged to filter the amplified signal and output a filtered signal. The comparing circuit is coupled to the filtering circuit and arranged to compare the filtered signal to a reference voltage and output an output signal indicating the noise level of the circuit to be detected.