On-Chip Multi-Bank NVM with Dynamic Back Biasing for Leakage and Latency
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Solution Overview
Problem
On-chip multi-bank non-volatile memory (NVM) structures suffer from significant leakage power consumption during standby states due to large memory banks, and switching to a deep power down mode to reduce leakage increases data access latency when powering back up.
Innovation Solution
A hierarchical memory architecture with an on-chip multi-bank NVM structure that includes well regions in a semiconductor substrate, an insulator layer, and a bias control circuit to independently switch back biasing voltages between reverse and forward modes based on access requests and cache data retrieval processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If memory banks are switched to deep power down mode to reduce leakage power consumption, then power consumption is reduced, but data access latency increases when powering back up
Solution Approach 1:
The patent implements dynamic power management by switching memory banks between different power states (deep power down mode and operational mode) based on access patterns. The bias control circuit dynamically adjusts back biasing voltages to transition banks between these states, optimizing the balance between power consumption and access latency.
Solution Approach 2:
The system performs preliminary actions by pre-charging or pre-activating memory banks before actual data access is needed. The bias control circuit can apply forward back biasing voltages in advance to prepare banks for quick activation, reducing the effective latency when data access is required.
2Quantity of substance
If large memory banks are used in multi-bank NVM structures, then storage capacity is increased, but leakage power consumption during standby state increases
Solution Approach 1:
The patent divides the large NVM structure into multiple independent memory banks, each with its own well region and bias control. This segmentation allows individual banks to be powered down independently when not in use, reducing total leakage power consumption while maintaining overall storage capacity.
Solution Approach 2:
Different power management strategies are applied to different memory banks based on their usage patterns. The bias control circuit can apply reverse back biasing voltages to standby banks to minimize leakage, while maintaining forward biasing for active banks, creating localized optimal conditions for each bank.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces leakage power consumption while minimizing data access latency by selectively applying forward and reverse back biasing voltages to NVM banks, ensuring optimal power management and performance.
Implementation Method 1
The bias control circuit can output back biasing voltages for the memory banks to the well regions. The bias control circuit can further independently switch these back biasing voltages between a reverse back biasing voltage and a forward back biasing voltage.
Implementation Method 2
The bias control circuit can further independently switch these back biasing voltages between a reverse back biasing voltage and a forward back biasing voltage.
Data Source
AI summary
A disclosed non-volatile memory (NVM) structure is implemented in a fully depleted semiconductor-on-insulator technology processing platform and includes multiple NVM banks with NVM cells including transistors. NVM banks have well regions in a substrate. Transistors of NVM cells of each NVM bank are on an insulator layer above a corresponding well region for that bank. A bias control circuit causes well regions for NVM banks in a standby state to be biased with a reverse back biasing voltage and causes a well region for an NVM bank in an operational state to be biased with a forward back biasing voltage. The bias control circuit can initiate forward back biasing during a cache data retrieval process (before NVM bank access) to ensure that the corresponding well region of an NVM bank at issue is fully biased when, following the cache data retrieval process, access to the NVM bank is still required.