On-Chip Packet Processing for Circuit Testing
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Solution Overview
Problem
The increasing complexity and speed of integrated circuit (IC) devices pose challenges for manufacturers in ensuring reliable high-speed links and timely, cost-effective testing and validation, particularly in securely providing firmware updates, due to decreased link reliability.
Innovation Solution
The implementation of on-chip packet processing functionality, including a protocol stack that detects isochronous timestamp packets, modifies non-deterministic data with substitute information, and generates signature information for evaluating circuit performance, using link control logic to emulate signals and selectively disable communication with the analog physical layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If on-chip packet processing functionality is implemented to enable circuit testing, then testing efficiency and reliability are improved, but device complexity increases
Solution Approach 1:
The protocol stack is designed to perform both normal data processing and test packet processing functions. The same packet processing circuitry handles both production traffic and test packets, allowing the system to serve multiple purposes without adding separate dedicated test hardware, thus improving reliability while controlling complexity.
Solution Approach 2:
A link controller acts as an intermediary between the physical layer and higher protocol layers. It manages the injection of test packets into the data path and coordinates the interaction between test and production modes, enabling reliable testing while maintaining clear separation of concerns and manageable system complexity.
2Reliability
If comprehensive circuit testing and validation are performed, then product reliability is improved, but manufacturing time and cost increase
Solution Approach 1:
Testing functionality is built into the device during manufacturing, allowing test packets to be injected and processed through the complete data path before final product completion. This preliminary testing approach validates circuit performance early in the manufacturing process, ensuring reliability while avoiding time-consuming post-assembly testing procedures.
Solution Approach 2:
The device performs self-testing by processing test packets through its own protocol stack and data path without requiring external test equipment. The packet processing circuitry evaluates its own performance by analyzing test packets that traverse the complete communication path, enabling rapid validation during manufacturing and improving productivity while maintaining high reliability standards.
Data Source
AI summary
Techniques and mechanisms to modify packet information in support of on-chip test functionality. In an embodiment, an integrated circuit (IC) chip includes a protocol stack to receive and process packetized information—e.g., where the processing of at least one isochronous timestamp packet (ITP) includes circuitry of the protocol stack replacing non-deterministic data of the ITP with substitute information. A deterministic nature of the substitute information enables the subsequent generation of corresponding signature information which can be used in an evaluation of circuit performance. In another embodiment, the ITP packet is modified at a transaction layer of the protocol stack, and the signature information is determined with an accumulator circuit which is part of another layer of the protocol stack.