On-Chip PLL Reference Clocking for Dynamic Frequency Scaling
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Solution Overview
Problem
Conventional computer architectures rely on external clock control logic for overclocking or underclocking CPU dies, which requires additional resources and is constrained by the type of interconnects used, limiting the maximum allowable frequency of the base clock signal.
Innovation Solution
An integrated circuit (IC) chip generates a reference clock signal locally based on a cyclical signal from an external source, enabling automatic updates to the clock frequency through phase-locked loop (PLL) circuitry and voltage regulation, allowing a wider range of frequencies and dynamic adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If external clock control logic is used for overclocking or underclocking CPU dies, then clock frequency adjustment is enabled, but additional conductive contacts, interconnects and resources are required
Solution Approach 1:
The patent extracts the clock control logic from external components and relocates it entirely within the CPU die. The on-die clock control logic receives a reference clock signal from an external source and generates adjusted clock signals for various synchronous domains, eliminating the need for external clock control logic and its associated conductive contacts and interconnects.
Solution Approach 2:
The patent merges the clock control functionality with the CPU die by integrating on-die clock control logic. This consolidation combines the functions of external clock control logic, frequency adjustment mechanisms, and clock distribution into a single integrated unit on the CPU die, reducing system complexity.
2Speed
If external clock control logic is used, then clock frequency control is achieved, but the system is constrained by the type of interconnect which limits maximum allowable frequency
Solution Approach 1:
The patent removes the frequency-limiting constraint by extracting the clock frequency adjustment functionality from the external interconnect domain and placing it on the CPU die. The on-die clock control logic can adjust clock frequencies for different synchronous domains independently of the reference clock signal frequency, allowing operation beyond the interconnect's maximum frequency limit.
Solution Approach 2:
The patent implements dynamic frequency adjustment capability where the on-die clock control logic can independently set different clock frequencies for different synchronous domains based on operational requirements. This dynamic control allows the system to adapt clock frequencies in real-time without being constrained by fixed interconnect limitations.
3Adaptability or versatility
If on-chip generation of reference clock signal is implemented, then frequency constraints are overcome and dynamic adjustments are enabled, but additional on-chip circuitry is required
Solution Approach 1:
The patent merges multiple clocking functions into the on-die clock control logic, including reference clock signal generation, frequency adjustment, and distribution to multiple synchronous domains. This consolidation reduces the need for separate external clock control logic and interconnect structures, making the added on-chip circuitry worthwhile.
Solution Approach 2:
The on-die clock control logic is designed as a universal component that can generate and adjust clock signals for multiple different synchronous domains within the CPU die. This multi-functional approach allows a single piece of on-chip circuitry to serve multiple purposes, reducing the overall complexity compared to having separate external clock control for each domain.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution allows for a more flexible and efficient clocking system, overcoming frequency constraints and enabling dynamic frequency adjustments without the need for external clock control logic, thereby supporting higher operational frequencies in computer architectures.
Implementation Method 1
with phase-lock loop (PLL) circuitry of the first circuit, generating a clock signal based on both the cyclical signal and a supply voltage provided to the PLL circuitry
Implementation Method 2
regulating the supply voltage with a control signal based on the evaluation, comprising automatically changing a level of the supply voltage in response to the control signal
Data Source
AI summary
Techniques and mechanisms for an integrated circuit (IC) chip to generate a clock signal for use by one or more resources of the IC chip. In an embodiment, a clock signal is generated with phase-locked loop (PLL) circuitry of an IC chip based on a cyclical signal which is provided to the IC chip by an external source. A supply voltage provided to the PLL circuitry is automatically updated based on one of a requested frequency for the clock signal, a frequency of the received cyclical signal, or a voltage of a control signal used by a voltage controlled oscillator of the PLL circuitry. In another embodiment, a series of incremental changes to a frequency of the clock signal is automatically performed according to a predefined overclocking scheme or underclocking scheme.