On-Chip POR Pulse Circuits for Low-Noise SoC Reset Timing
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Solution Overview
Problem
Reducing the area and complexity of on-chip circuits that generate power on reset (POR) pulses while minimizing inter-module and inter-chip noise is challenging in System on Chips (SoCs).
Innovation Solution
The integration of a power supply sense circuit, pulse generation circuit, and reset generation circuit, utilizing voltage dividers, MOS transistors, inverter circuits, delay blocks with Miller amplifiers, and Schmitt trigger buffers to generate a POR pulse of specific duration for resetting circuit elements, such as flip-flops and memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If POR pulse is generated external to the chip, then inter-module and inter-chip noise is reduced, but area and complexity of on-chip circuits increases
Solution Approach 1:
The patent combines multiple functions (power supply sensing, POR pulse generation, and reset signal generation) into a single integrated on-chip circuit block. The power supply sense circuit detects power transitions, triggers the pulse generation circuit to create POR pulses, and the reset generation circuit distributes reset signals to multiple elements simultaneously. This merging eliminates the need for external POR generation while reducing noise and maintaining compact area.
Solution Approach 2:
The on-chip circuit is designed to perform multiple functions: sensing power supply transitions, generating POR pulses with specific duration, and distributing reset signals to multiple circuit elements. This multi-functional design replaces what would traditionally require separate external components, reducing both area and noise while maintaining comprehensive reset capability across the chip.
2Object-affected harmful factors
If POR pulse is generated external to the chip, then noise is reduced, but device complexity increases
Solution Approach 1:
The patent integrates power supply sensing, POR pulse generation, and reset signal distribution into a single unified on-chip circuit. This consolidation reduces device complexity by eliminating the need for external POR generation circuits and multiple separate control circuits, while simultaneously reducing inter-chip noise by keeping all functions on-chip.
3Object-affected harmful factors
If on-chip POR pulse generation is implemented, then noise is reduced, but area and complexity increase
Solution Approach 1:
The patent merges power supply sensing, POR pulse generation, and reset signal distribution into a single integrated on-chip block, achieving noise reduction while minimizing area through functional consolidation.
Solution Approach 2:
The on-chip circuit performs multiple functions (sensing, pulse generation, signal distribution) simultaneously, reducing the need for separate components and minimizing overall circuit area while maintaining low noise performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables efficient on-chip generation of POR pulses with reduced area requirements and noise margins, ensuring proper resetting of circuit elements while maintaining independence from power sequencing of secondary supplies.
Implementation Method 1
a voltage divider circuit comprising a first resistor and a second resistor coupled or positioned between a power supply and a reference supply. The voltage divider circuit is configured to generate a first signal proportional to the power supply signal at a node between the first resistor and the second resistor.
Implementation Method 2
The MOS transistor is configured to assert or transmit a second signal at the third terminal upon, or in response to, the first signal being greater than a threshold voltage.
Implementation Method 3
The inverter circuit is configured to (1) receive the second signal at gate terminals of the at least one PMOS transistor and the at least one NMOS transistor and (2) generate the sense signal at an output terminal of the inverter circuit in response to the second signal and the power supply signal.
Implementation Method 4
The delay block further comprises an amplifier circuit (e.g., a Miller amplifier) comprising an inverting voltage amplifier and a miller capacitor coupled or positioned between an input node and an output node of the inverting voltage amplifier, wherein the charging and discharging of an equivalent capacitor at the input node of the inverting voltage amplifier is configured to generate a pulse of a pre-determined width or duration at the output node of the amplifier.
Data Source
AI summary
Integrated Circuits (ICs) comprising circuits configured to generate a power on reset (POR) pulse are disclosed. An IC comprises a power supply sense circuit configured to generate a sense signal in response to a transition of a power supply signal from a first level to a second level, and a pulse generation circuit coupled with the power supply sense circuit. The pulse generation circuit is configured to generate a power on reset (POR) pulse of a threshold duration based on the sense signal. The IC further includes a reset generation circuit coupled with the pulse generation circuit to receive the POR pulse. The reset generation circuit is configured to generate a reset pulse based on the POR signal and of at least one control signal, where the reset pulse is configured to be utilized to perform a reset of one or more elements of the integrated circuit.