On-Chip Power Management with Masking Block
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
On-chip power regulators face challenges in providing reliable and stable supply voltages due to their dependency on the digital core, leading to unreliable system operation and increased packaging costs from additional IO pads required for control signals, which hinders testing and efficiency.
Innovation Solution
A power management device with a power regulator block and masking block, including a power on reset circuit, bandgap reference generator, and low voltage detectors, that enables or disables the regulator based on control signals from the digital logic core, ensuring stable voltage levels and initialization before system operation, allowing for safe startup and testing of sub-blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the control signal is provided from the IO ring, then the on-chip regulator can be controlled, but the number of IO pads increases resulting in increased packaging cost
Solution Approach 1:
The patent combines the control signal generation function with the existing digital core logic. The digital core, which already exists for system operation, is enhanced to generate the control signal for the on-chip regulator, eliminating the need for separate IO pad connections for control purposes.
Solution Approach 2:
The digital core serves dual purposes: it performs the system's computational functions and simultaneously generates the control signal for the power regulator. This self-service approach allows the digital core to manage its own power regulation without external control inputs.
2Device complexity
If the digital core generates the control signal, then the number of IO pads is reduced, but the system operation becomes unreliable since the digital core operates on the Vdd supply generated by the regulator
Solution Approach 1:
The patent implements a startup sequence where the on-chip regulator is enabled first to generate a stable Vdd supply before the digital core is activated. This preliminary action ensures that when the digital core later generates the control signal, the regulator is already providing a reliable voltage reference.
Solution Approach 2:
Instead of the digital core controlling the regulator during normal operation, the patent inverts the control relationship during startup: the regulator is enabled first to establish a stable voltage, then the digital core takes control for normal operation. This inversion resolves the chicken-and-egg problem of dependency.
3Adaptability or versatility
If the on-chip regulator is used to generate Vdd from IO supply, then the number of off-chip supplies is reduced, but the system requires external power-up signals which increase device complexity
Solution Approach 1:
The on-chip regulator monitors its own input voltage and automatically enables itself when the IO supply reaches an adequate level. This self-service mechanism eliminates the need for external power-up control signals while maintaining the benefit of integrated power supply management.
Solution Approach 2:
The regulator incorporates voltage monitoring that provides feedback about the IO supply status. When the monitored voltage reaches a threshold indicating adequate power availability, the regulator automatically activates, creating a closed-loop system that responds to power conditions without external control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a stable regulated supply voltage, reduces packaging costs, enhances testability, and ensures reliable system operation by initializing the IC safely without external power-up signals, facilitating Design For Test (DFT) and debugging while avoiding time delays and external control signals.
Implementation Method 1
The power regulator block includes any one or more of the following elements—voltage regulator, bandgap reference generator, and low voltage detector
Implementation Method 2
a power regulator block capable of being enabled or disabled by one or more control signals
Implementation Method 3
low voltage detector
Data Source
AI summary
The present disclosure teaches a power management device for providing one or more voltages and prohibiting the operation until the IC is initialized and voltage stability is achieved. The power management device includes a power regulator block and a masking block. The power regulator block includes one or more of the following elements:- a regulator, a bandgap reference generator, a low voltage detector LVDD, a low voltage detector LVDM, and a plurality of logic gates. In one embodiment, the masking block includes one or more level shifters, a plurality of logic gates, a D flip-flop, and a power on reset circuit (PoR).