On-Chip Queue Management for Network Adapter Packet Descriptors
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Solution Overview
Problem
Conventional network adapter architectures face performance limitations due to slow access times for external memory resources and data coherency issues when managing packet queues, particularly in managing linked lists of packet descriptors across on-chip and off-chip memory.
Innovation Solution
Implementing a network adapter architecture with on-chip queue management logic and linking memory resources, where queue management logic maintains indices to descriptors stored in linking memory, reducing the need for frequent external memory access and enhancing data coherency by using queue registers and linking RAM to manage packet queues efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional network adapter architectures use external memory resources to store packet descriptors, then memory capacity is increased, but access speed decreases due to slower external memory access times
Solution Approach 1:
The patent segments memory resources into on-chip memory for frequently accessed queue management data and off-chip memory for bulk packet descriptor storage. This segmentation allows the system to maintain fast access for critical operations while utilizing large capacity for overall storage needs.
Solution Approach 2:
The patent introduces a descriptor index structure that acts as an intermediary between the queue management logic and packet descriptors in external memory. This index maintains references to packet descriptors in on-chip memory, reducing the need for direct external memory access and improving access speed while maintaining the ability to store large quantities of descriptors externally.
2Adaptability or versatility
If conventional architectures manage packet queues using linked lists in external memory, then queue management flexibility is improved, but data coherency issues arise between on-chip and off-chip memory
Solution Approach 1:
The descriptor index serves as an intermediary layer that maintains coherent references to packet descriptors. By storing indices in on-chip memory that point to packet descriptors in off-chip memory, the system maintains data coherency without sacrificing the flexibility to manage queues across memory boundaries.
Solution Approach 2:
The system performs preliminary actions by pre-loading frequently accessed packet descriptor indices into on-chip memory before they are needed for queue operations. This ensures that when queue management operations occur, the necessary data is already available in fast memory, maintaining coherency and performance.
3Ease of operation
If frequent external memory access is used for queue management operations, then queue management functionality is maintained, but performance deteriorates due to slow external memory access
Solution Approach 1:
The patent segments queue management operations into two categories: those requiring on-chip memory access for immediate processing and those that can utilize off-chip memory through the descriptor index mechanism. This segmentation allows the system to maintain full functionality while optimizing performance by minimizing slow external memory accesses.
Solution Approach 2:
The patent creates a copy of the packet descriptor information in the form of an index structure in on-chip memory. This index copy contains the necessary references and metadata to access the actual packet descriptors in off-chip memory, allowing queue management operations to proceed using fast on-chip memory while maintaining access to the full external memory storage capacity.
Data Source
AI summary
A network element including a processor with logic for managing packet queues by way of packet descriptor index values that are mapped to addresses in the memory space of the packet descriptors. A linking memory is implemented in the same integrated circuit as the processor, and has entries corresponding to the descriptor index values. Each entry can store the next descriptor index in a packet queue, to form a linked list of packet descriptors. Queue manager logic receives push and pop requests from host applications, and updates the linking memory to maintain the queue. The queue manager logic also maintains a queue control register for each queue, including head and tail descriptor index values.