On-Chip RF Shield Using Interconnect Metallization
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Solution Overview
Problem
The integration of multiple components on a single chip in semiconductor devices leads to interference issues due to electromagnetic radiation from RF circuitry operating at high frequencies, which worsens with each technology generation, necessitating a solution that does not significantly increase production costs.
Innovation Solution
The implementation of an on-chip RF shield using interconnect metallization, where a conductive shield formed from back-end metallization layers surrounds RF components to block electromagnetic radiation, minimizing interference with other components while sharing manufacturing steps with existing chip fabrication processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If separate shielding layers or structures are added to block electromagnetic radiation, then electromagnetic interference between RF and other components is reduced, but fabrication costs and device complexity increase
Solution Approach 1:
The patent combines the RF shielding function with the existing interconnect metallization layers that are already part of the chip fabrication process. Instead of adding separate shielding layers, the invention uses the same metal layers (such as M5, M6, M7) that are deposited for electrical interconnections to also serve as electromagnetic shields. This merging of functions eliminates the need for additional shielding materials and fabrication steps, thereby reducing device complexity and fabrication costs while still providing effective electromagnetic interference protection.
2Object-affected harmful factors
If separate shielding layers or structures are added to block electromagnetic radiation, then electromagnetic interference between RF and other components is reduced, but production costs increase
Solution Approach 1:
The patent merges the RF shielding function with the existing interconnect metallization process. The same metal deposition steps (such as sputtering or electroplating of copper, aluminum, or tungsten) that are used to create electrical interconnections are also used to form the shielding structures. This eliminates the need for separate material purchases, additional deposition equipment, and extra fabrication steps, thereby significantly reducing production costs while achieving effective electromagnetic interference protection.
3Object-affected harmful factors
If additional shielding structures are added, then electromagnetic interference is reduced, but chip area available for circuitry decreases
Solution Approach 1:
The patent makes the interconnect metallization layers serve multiple functions: electrical interconnection and electromagnetic shielding. The same metal layers that connect different circuit components are also configured to provide shielding over RF circuits. By making the shielding function universal to the existing interconnect structure, no additional chip area is consumed for dedicated shielding elements, as the shielding is provided by the interconnect metals themselves that would exist anyway for electrical connections.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces electromagnetic interference between RF and other components on the chip, maintaining minimal noise generation and immunity to received noise, without the need for separate shielding layers or structures, thus avoiding additional fabrication costs and area penalties.
Implementation Method 1
An interconnect RF barrier is disposed between the RF circuitry and the semiconductor circuitry, the interconnect RF barrier coupled to a ground potential node
Data Source
AI summary
Structure and method for fabricating a system on chip with an on-chip RF shield including interconnect metallization is described. In one embodiment, the system on chip includes an RF circuitry disposed on a first portion of a top surface of a substrate, and a semiconductor circuitry disposed on a second portion of the top surface of the substrate. An interconnect RF barrier is disposed between the RF circuitry and the semiconductor circuitry, the interconnect RF barrier coupled to a ground potential node.