On-Chip Self-Trim Circuitry for Parallel Calibration Testing
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Solution Overview
Problem
Existing semiconductor chip calibration and testing methods require serial trimming operations, which are time-consuming and inefficient, as they rely on automatic test equipment (ATE) to individually calculate and apply trim values to each chip, limiting parallel testing capabilities.
Innovation Solution
Integration of self-trim and self-test circuitry on the chip, utilizing a state machine to autonomously perform trimming and testing, including an LSB offset to determine and store trim values independently of ATE, allowing parallel processing of trimming and testing operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If serial trimming operations are performed using ATE to individually calculate and apply trim values to each chip, then trimming accuracy is improved, but test time increases and productivity decreases
Solution Approach 1:
The patent implements self-trim circuitry on each chip that autonomously performs trimming operations without requiring external ATE intervention. The on-chip state machine calculates trim values and adjusts analog circuit parameters independently, allowing parallel processing of multiple chips simultaneously. This self-service approach maintains trimming accuracy while dramatically reducing test time and increasing productivity.
Solution Approach 2:
The patent extracts the trimming function from the external ATE system and relocates it onto the chip itself through integrated self-trim circuitry. By taking out the trimming operation from the centralized ATE and distributing it to individual chips, the system enables parallel trimming of multiple chips, resolving the contradiction between accuracy and productivity.
2Manufacturing precision
If ATE is used to perform individual trimming calculations and apply trim values to each chip, then trim precision is improved, but device complexity and resource requirements increase
Solution Approach 1:
Each chip is equipped with self-trim circuitry including state machines and analog adjustment circuitry that autonomously perform trimming operations. This distributes the trimming intelligence from a complex centralized ATE system to simple, self-contained on-chip modules, reducing overall system complexity while maintaining trim precision.
Solution Approach 2:
The patent replicates the trimming functionality across multiple chips by integrating identical self-trim circuitry blocks on each chip. Instead of using a single complex ATE to manage all trimming operations, the system copies the trimming capability to each individual chip, enabling parallel operation and reducing the complexity of the external testing infrastructure.
3Measurement precision
If serial trimming operations are performed on each chip individually, then measurement accuracy is improved, but the quantity of chips that can be tested in parallel decreases
Solution Approach 1:
Each chip performs its own trimming operations independently using on-chip self-trim circuitry, allowing multiple chips to be trimmed simultaneously without interfering with each other's measurement accuracy. This self-service capability enables parallel processing while maintaining the precision that would otherwise require serial operation.
Solution Approach 2:
The patent divides the trimming function into independent, self-contained segments on each chip. Instead of a centralized serial trimming process, each chip has its own segmentation of the trimming functionality, allowing simultaneous operation of multiple chips and increasing the quantity of chips that can be tested in parallel while preserving measurement precision.
Data Source
AI summary
A self-trim circuit provides a technique to trim a CUT (circuit under trim) using a LSB offset to determine the best digital value to trim the CUT. The self-trim circuit is also used to self-test the digital and analog portions of the self-trim circuitry, whereby the existence of a digital stuck at fault condition is detected. A state machine controls a digital stack to couple digital trim data to the CUT and read the output of a comparator circuit that signifies when a proper digital trim value has been used. Thereafter the proper digital trim value is stored into a nonvolatile memory.