On-Chip Sequence Profiler for Bit Execution Verification
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Solution Overview
Problem
Current electronic circuits lack effective means to guarantee the exact execution of software sequences on hardware and to identify any deviations or failures in the order of circuit elements, which hampers debugging and fault identification.
Innovation Solution
An on-chip sequence profiler is introduced, comprising checkpoint elements like latches and multiplexers coupled with a logic circuit, which generates a programmable matrix to track bit sequences and determine if they are executed correctly, allowing for successful execution tracking and debugging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If an on-chip sequence profiler is implemented to track and verify bit sequence execution, then measurement precision and reliability are improved, but device complexity increases due to additional checkpoint elements (latches, multiplexers, logic circuits)
Solution Approach 1:
The sequence profiler is divided into multiple independent checkpoint elements (latches, multiplexers, logic circuits) that can be distributed throughout the circuit. Each checkpoint monitors specific portions of the bit sequence independently, allowing the verification function to be segmented across multiple simple units rather than one complex centralized monitor.
Solution Approach 2:
Checkpoint elements are introduced as intermediary components between the scan path and functional paths. These intermediaries capture and compare bit values without disrupting the primary data flow, enabling verification while maintaining normal circuit operation through controlled signal interception and comparison.
2Reliability
If checkpoint elements are added to monitor and verify bit sequences in real-time, then reliability is improved, but loss of time increases due to additional signal routing and comparison operations
Solution Approach 1:
Expected bit sequence values are pre-loaded into the programmable matrix before the actual sequence execution begins. This allows the logic circuits to immediately compare incoming bits against predetermined expectations without requiring real-time computation of what the sequence should be, reducing verification delay.
Solution Approach 2:
The expected bit sequence is copied into the programmable matrix as reference data. Instead of computing expectations during verification, the system uses pre-copied reference values for direct comparison, enabling fast reliability checks through simple bitwise comparison operations rather than complex real-time analysis.
3Measurement precision
If the profiler captures and compares all bit sequences to expected values, then measurement precision is improved, but use of energy increases due to continuous operation of latches, multiplexers, and logic circuits
Solution Approach 1:
The profiler can be configured to monitor only critical portions of the bit sequence rather than every single bit. By selectively enabling checkpoints for important data paths or key sequence elements, the system achieves sufficient measurement precision for verification purposes while reducing the number of active comparison operations and associated energy consumption.
Data Source
AI summary
A method, circuit, and design structure for an on-chip sequence profiler involves a programmable matrix and FSM in a logic circuit, a first latch receiving a scan path bit sequence and a first clock signal and generating a first output to control a select input of a first multiplexer, a first multiplexer selecting among functional path bit sequences and outputting a bit sequence to a second latch, a second latch receiving the bit sequence from the first multiplexer and a second clock signal via a second multiplexer and outputting a bit sequence to a logic circuit, a logic circuit receiving the bit sequence from the second latch and outputting a clock control signal to the clock and a second selector control signal to the second multiplexer, and a second multiplexer receiving a second clock signal from the clock and outputting the second clock signal to the second latch.