On-Chip SerDes for Dual-Protocol PHY via Passive Channel

The patent extracts the essential function of data alignment from the complex flip-flop pipelining structure and implements it through a simplified timing recovery mechanism using delay-locked loops (DLL) and buffer adjustment. This removes the bulky flip-flop infrastructure while retaining the core functionality of skew compensation.

The patent changes the approach from static flip-flop-based alignment to dynamic parameter adjustment using DLL-controlled timing recovery. The system adjusts buffer read/write pointers and delay elements based on detected skew parameters, enabling adaptive alignment without fixed pipelining structures.

The patent removes the power-hungry flip-flop pipelining infrastructure and replaces it with a low-power timing recovery mechanism using DLLs and programmable buffers. This extraction eliminates unnecessary switching activity while maintaining data alignment functionality.

The system implements self-adjusting timing recovery where the DLL automatically detects and compensates for skew without requiring high-power external control logic. The buffers self-regulate their read/write timing based on incoming data characteristics, reducing overall power consumption.

The patent transitions from fixed-stage flip-flop delay to continuously adjustable buffer timing controlled by DLLs. This allows dynamic optimization of delay parameters to match actual skew measurements, minimizing latency while achieving complete skew compensation.

The system employs dynamic timing adjustment where buffer pointers and delay elements are continuously adapted based on real-time skew detection. This replaces the static, over-engineered flip-flop pipeline with a flexible, demand-based timing mechanism that introduces only necessary delay.

The patent implements a universal PHY interface that can directly accept data streams from multiple controllers (DP, USB3, etc.) without requiring protocol-specific multiplexing logic. The interface is designed to handle different protocols simultaneously through standardized timing recovery and deserialization mechanisms, reducing overall system complexity.

The patent segments the data transmission path into independent protocol-handling modules that feed into a common PHY interface. Each controller maintains its own data path to the PHY, eliminating the need for complex centralized multiplexing while allowing efficient parallel operation of multiple protocols.