On-Chip Signal Generator for Scan Chain Test Pattern Generation
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Solution Overview
Problem
Existing burn-in test methods face challenges with limited space for ATPG pattern storage and complex signal routing requirements, necessitating a reduction in signal routing efforts during the test mode for integrated circuits.
Innovation Solution
An on-chip signal generator is integrated with the chip to provide a test pattern signal to scan chains, eliminating the need for external signal routing and simplifying the test setup by using a linear feedback shift register or decompressor, which reduces the complexity and cost of the signal generator.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If external ATPG pattern storage and signal routing are used, then comprehensive logic element testing is achieved, but space requirements and routing complexity increase
Solution Approach 1:
The patent merges the external ATPG pattern generator and storage functions into an on-chip linear feedback shift register (LFSR). This integration consolidates multiple external components into a single on-chip unit, eliminating complex external signal routing while maintaining comprehensive logic element testing capability through the LFSR's ability to generate pseudorandom test patterns internally.
Solution Approach 2:
The on-chip LFSR generates its own test patterns autonomously without requiring external ATPG equipment. The feedback taps and XOR gates within the LFSR automatically produce the pseudorandom sequence needed for testing, enabling the chip to self-test its logic elements without external intervention for pattern generation.
2Ease of operation
If external ATPG patterns are stored and routed, then test patterns can be provided, but test setup time and routing efforts increase
Solution Approach 1:
The patent combines the pattern storage and pattern generation functions into a single on-chip LFSR structure. This eliminates the need for separate external pattern storage devices and complex routing infrastructure, dramatically reducing test setup time and simplifying the testing process to merely initializing the LFSR and enabling scan mode.
3Device complexity
If on-chip signal generator is used, then signal routing complexity is reduced, but on-chip space is required for the generator
Solution Approach 1:
The on-chip LFSR utilizes feedback connections from existing on-chip logic elements to generate test patterns. By tapping into outputs from the scan chains or logic elements themselves and feeding them back through XOR gates, the system generates comprehensive test patterns using minimal additional on-chip resources, effectively using the chip's own structure to serve the testing function.
Data Source
AI summary
A chip is provided that includes an integrated circuit including a plurality of logic elements, wherein the plurality of logic elements is configured to form, in a test mode, a plurality of scan chains. The chip further includes an on-chip signal generator connected with the integrated circuit and configured to provide, in the test mode, a test pattern signal to the plurality of scan chains.