On-Chip Star Network for I/O Pad Testing
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Solution Overview
Problem
The high cost and complexity of automated test equipment (ATE) systems for integrated circuits with high I/O pad counts lead to limited availability and increased testing time due to the need for numerous ATE test channels, and the use of mechanical relays results in higher test costs and shorter load board lifespan.
Innovation Solution
Implementing an on-chip star network with test multiplexers, digital-to-analog converters, and wide-range comparators allows for efficient IO leakage and DC parametric testing using fewer ATE test channels, enabling lower-cost, more accessible ATE systems and reducing test time by sharing test circuitry among multiple I/O pads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of ATE test channels is increased to test each I/O pad individually, then testing coverage is improved, but system cost increases significantly
Solution Approach 1:
Multiple I/O pads are merged into a single test group that shares common test circuitry including the star network, DAC, comparator, and control logic. This allows one ATE test channel to perform tests on multiple I/O pads simultaneously, reducing the total number of ATE channels needed while maintaining comprehensive test coverage.
Solution Approach 2:
The test circuitry is designed with universal functionality to handle multiple I/O pads through the star network architecture. The same DAC, comparator, and control circuitry serve multiple pads by dynamically configuring connections via the star network, eliminating the need for dedicated test channels for each pad.
2Device complexity
If mechanical relays are used in load boards to reduce ATE channel requirements, then equipment cost is reduced, but test time increases due to relay response time
Solution Approach 1:
The mechanical relay system is replaced with an on-chip star network implemented using electronic switches or multiplexers integrated into the semiconductor device. This electronic implementation eliminates the mechanical moving parts and associated response time delays while maintaining the ability to dynamically configure test connections.
Solution Approach 2:
The star network acts as an intermediary between the ATE test channel and multiple I/O pads, providing rapid electronic switching capability. This intermediary structure enables fast reconfiguration of test connections without the time penalties associated with mechanical relay operation.
3Device complexity
If mechanical relays are used in load boards, then ATE channel requirements are reduced, but load board lifespan decreases due to relay wear
Solution Approach 1:
The mechanical relay system is replaced with solid-state electronic switching implemented through the on-chip star network. This eliminates wear-prone mechanical components and extends the operational life of the test system, as electronic switches have no moving parts and can operate indefinitely within their electrical specifications.
Solution Approach 2:
The star network is integrated directly into the semiconductor device under test, making the switching functionality self-contained within the device itself. This eliminates the need for external mechanical relays in the load board, transferring the switching function to the device under test and thereby extending overall system lifespan.
4Device complexity
If one ATE test channel tests multiple I/O pads via mechanical relays, then equipment cost is reduced, but test cycle time increases
Solution Approach 1:
Mechanical relays are replaced with integrated on-chip electronic switching through the star network. This substitution enables much faster connection reconfiguration between the ATE test channel and different I/O pads, reducing the time required to cycle through multiple test configurations and thereby improving overall test cycle time.
Solution Approach 2:
The star network is pre-configured within the device structure with all switching paths available in advance. This preliminary preparation of the switching architecture allows immediate reconfiguration without mechanical delay, enabling the ATE system to rapidly sequence through multiple I/O pads without the time penalties of mechanical relay operation.
Data Source
AI summary
One embodiment of the present invention sets forth an integrated circuit that includes multiple input/output (I/O) pad groups. Each I/O pad group includes an on-chip star network, multiple I/O pads, multiple test multiplexers, a digital-to-analog converter (DAC), and a wide-range comparator. Each test multiplexer is configured to couple a different I/O pad to the on-chip star network. The DAC is configured to supply at least one of a source current, a sink current, and a first reference voltage to the on-chip star network. The wide-range comparator is configured to compare a voltage present on a first I/O pad included in the plurality of I/O pads with a second reference voltage. Advantageously, IO leakage and DC parametric testing may be performed on integrated circuits with high I/O pad counts using an ATE system with a significantly lower quantity of ATE test channels relative to prior approaches.