On-Chip Statistical Characterization Circuit for CMOS Variations
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Solution Overview
Problem
Traditional methods for statistical characterization of CMOS process structures and MOS devices are inefficient and time-consuming, as they rely on outdated paradigms that do not account for random local variability and manufacturing variations, leading to insufficient statistical confidence and prolonged measurement times, making it economically unfeasible to characterize electrical characteristics accurately.
Innovation Solution
A circuit architecture with an on-chip programmable ramp voltage generator, dual input 9-11 bit cyclic ADC, and a 2 Kb latch bank, synchronized by a dual phase clock, enables rapid and accurate statistical characterization of electrical variations by stimulating and measuring devices on-chip, eliminating the need for off-chip communication and reducing measurement time significantly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional parametric testers are used for DC measurement, then measurement accuracy is maintained, but measurement time becomes excessively long (several hundred milliseconds to over a second per measurement)
Solution Approach 1:
The patent replaces traditional off-chip parametric testers with an on-chip measurement system that integrates the ADC, stimulus generator, and latch bank directly on the semiconductor device. This substitution eliminates the need for external testing equipment and enables parallel measurement of multiple devices simultaneously, reducing measurement time from seconds to milliseconds while maintaining measurement accuracy through precise on-chip voltage generation and digital conversion.
Solution Approach 2:
The patent merges multiple previously separate components (stimulus generator, ADC, latch bank, and device under test) into a single integrated on-chip system. This consolidation allows simultaneous operation of multiple measurement channels, enabling parallel characterization of numerous devices or process structures on a single chip, thereby dramatically increasing throughput while preserving measurement precision through coordinated operation of integrated components.
2Reliability
If sufficient sample sizes are used for statistical characterization (at least a few thousand repetitions), then statistical confidence is improved, but the time consumed becomes very significant (400 days for a single lot)
Solution Approach 1:
The patent implements continuous parallel measurement operations where multiple devices are characterized simultaneously across numerous measurement channels operating in parallel. This continuous concurrent operation enables collection of statistically significant data from thousands of devices within hours rather than hundreds of days, as each measurement channel continuously gathers data without sequential delays.
Solution Approach 2:
The patent segments the measurement system into multiple independent parallel measurement channels, each capable of characterizing a device independently. This segmentation allows simultaneous characterization of many devices across the chip, transforming a sequential process that would take 400 days into a parallel process that completes in hours, while accumulating sufficient statistical samples for high-confidence characterization.
3Ease of operation
If conventional test pad structures are used, then measurement capability is provided, but chip area consumed becomes unworkable (proportional to number of devices tested)
Solution Approach 1:
The patent creates a universal on-chip measurement platform that can characterize multiple different device types and process structures using the same integrated ADC and stimulus generator. This multi-functional system replaces numerous dedicated test pad structures with a single reusable measurement core that serves all characterization needs, dramatically reducing chip area while maintaining full measurement capability across diverse device geometries and technologies.
Solution Approach 2:
The patent uses digital copying and representation of measurement data within the on-chip latch bank, allowing multiple measurements to be stored and processed without requiring additional physical test structures for each measurement instance. The digital latch bank captures and retains measurement results, enabling repeated analysis without consuming additional chip area, unlike conventional analog test pads that require physical duplication for each test case.
Data Source
AI summary
A Circuit architecture and a method for rapid and accurate statistical characterization of the variations in the electrical characteristics of CMOS process structures, MOS devices and Circuit parameters is provided. The proposed circuit architecture and method enables a statistical characterization throughput of <1 ms/DC sweep at <2 mV or <1 nA resolution accuracy of variations in voltage or current of the device under test. Salient features of proposed circuit architecture include a programmable ramp voltage generator that stimulates the device under test, a dual input 9-11 bit cyclic ADC that captures input and output DC voltage/current signals to/from the device under test, a 2 Kb latch bank that captures 9-11 bit streams for each measurement point in a DC sweep of programmable granularity and a clocking and control scheme that enables continuous measurement and stream out of digital data blocks from which the analog characteristics of the devices under test are reconstructed post measurement.