On-Chip Termination Calibration for Multi-Class Memory IO Banks
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Integrated circuit packages face challenges in supporting multiple classes of memory interfaces due to the need for different series and parallel termination impedance values, which current on-chip termination methods cannot accommodate within a single IO bank.
Innovation Solution
The implementation of an on-chip termination calibration circuit block that generates digital calibration codes, allowing for the adjustment of series and parallel termination impedance in input/output buffers by shifting the calibration code, enabling support for multiple classes of memory interfaces within a single IO bank.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single calibration circuit controls on-chip termination impedance in an IO bank, then circuit complexity is reduced, but the ability to support multiple classes of memory interfaces is lost
Solution Approach 1:
The patent divides the IO bank into multiple groups, with each group having its own calibration circuit that can independently control termination impedance. This segmentation allows different groups to support different memory interface classes (Class I, Class II, Class III) simultaneously while maintaining relatively simple individual circuit designs.
Solution Approach 2:
The patent implements dynamic calibration codes that can be shifted to adjust termination impedance values. The calibration circuits are designed to be reconfigurable, allowing the same hardware to adapt to different impedance requirements (25 ohms, 50 ohms, 75 ohms) based on the memory interface class being used.
2Reliability
If external termination resistors are used for each IO pin, then signal reflection is minimized, but the number of external components increases
Solution Approach 1:
The patent merges the termination resistance function into the on-chip buffer circuits. By integrating the termination resistors within the buffer itself, the patent eliminates the need for separate external termination resistors for each IO pin, thereby reducing external component count while maintaining signal integrity through proper impedance matching.
Solution Approach 2:
The on-chip buffers are designed to provide their own termination resistance through integrated resistive elements. This self-service approach allows each buffer to independently terminate its output signal, eliminating the need for external termination components and simplifying the overall system architecture.
3Quantity of substance
If on-chip termination is used to reduce external components, then component count is reduced, but the ability to support multiple memory interface classes is limited
Solution Approach 1:
The patent segments the IO bank into multiple groups, each with independent calibration circuits capable of supporting different memory interface classes. This allows the system to maintain reduced external component count while achieving versatility across multiple interface types through on-chip differentiation.
Solution Approach 2:
The patent uses programmable calibration codes that can be shifted to change the termination impedance parameters. By varying the calibration code values, the same on-chip circuit can adapt to support Class I (25 ohms), Class II (50 ohms), and Class III (75 ohms) memory interfaces, achieving multi-class support without increasing external component count.
Data Source
AI summary
Techniques are provided for individually adjusting the on-chip termination impedance that is generated by input and output (IO) buffers in an input/output (IO) bank on an integrated circuit. The IO buffers in an IO bank can generate different on-chip termination impedances. And as a result, an IO bank can support more than one class of memory interfaces. An OCT calibration block generates a digital on-chip termination (OCT) calibration code. In some embodiments, circuitry in the IO banks can be configured to shift the OCT calibration code by one or more bits to adjust the series and/or parallel on-chip termination impedance in one or more IO buffers.