On-Chip Termination Control for Flexible FPGA IO Bank Calibration
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Solution Overview
Problem
Integrated circuit packages face limitations in supporting high-speed memory interfaces due to the lack of calibrated on-chip termination in side IO banks, resulting in reduced performance compared to top and bottom IO banks.
Innovation Solution
Implementing on-chip termination (OCT) calibration techniques using OCT controllers that can calibrate impedance in all IO banks through shared or separate parallel buses, allowing any IO bank to receive control signals from any OCT controller, thus enabling flexible and ubiquitous OCT support across the chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If on-chip termination is implemented only in top and bottom IO banks, then high-speed memory interface performance is achieved in those banks, but side IO banks can only support lower performance interfaces
Solution Approach 1:
The patent implements a shared parallel bus architecture that allows any OCT controller to serve any IO bank on the chip. This universal control mechanism enables side IO banks to access calibrated termination control signals from OCT controllers, transforming them from limited-performance banks to high-speed capable banks, thereby achieving multi-functionality across all IO banks
Solution Approach 2:
The patent segments the OCT control functionality by introducing select logic or multiplexers in each IO bank that can independently select control signals from any OCT controller via the shared parallel bus. This segmentation allows flexible configuration where different IO banks can be dynamically assigned to different OCT controllers based on performance requirements
2Reliability
If external termination resistors are used for all IO pins, then signal reflection is minimized, but the number of external components increases significantly
Solution Approach 1:
The patent merges the termination resistance functionality into the on-chip IO buffers by integrating calibrated termination control circuits directly into the FPGA fabric. This consolidation eliminates the need for separate external termination resistors for each IO pin, reducing external component count while maintaining signal integrity through on-chip calibrated termination
3Adaptability or versatility
If calibrated on-chip termination is implemented in all IO banks, then all banks can support high-speed memory interfaces, but the complexity of OCT controller routing increases
Solution Approach 1:
The shared parallel bus architecture provides a universal communication pathway that simplifies routing complexity. Instead of requiring dedicated point-to-point connections between each OCT controller and each IO bank, the shared bus allows any controller to reach any bank through a common medium, reducing routing complexity while enabling universal access
Solution Approach 2:
The shared parallel bus acts as an intermediary that mediates between OCT controllers and IO banks. This intermediary structure simplifies the control signal routing by providing a standardized interface and selection mechanism (through multiplexers) that abstracts the complexity of direct connections
Data Source
AI summary
On-chip termination (OCT) calibration techniques are provided that support input/output (IO) banks on an integrated circuit (IC) using OCT controllers. The OCT controllers calibrate the on-chip termination impedance in the IO banks using a shared parallel bus or separate parallel buses. Multiplexers or select logic in each IO bank select control signals from the OCT controllers in response to select signals. According to some embodiments, each of the IO banks on an IC can receive OCT control signals from any of the OCT controllers on the IC.