Temperature-Independent On-Chip Termination Resistance
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Solution Overview
Problem
Conventional on-chip termination schemes in high-speed chip-to-chip communications systems face challenges due to non-linearities in the IV curve of on-chip termination resistance, leading to signal distortion and variations with process, voltage, and temperature (PVT) changes, which complicates impedance control and increases layout area and complexity.
Innovation Solution
An integrated circuit with a programmable termination scheme using resistive elements with positive and negative temperature coefficients of resistivity, where a sense element generates control signals to configure the termination scheme, maintaining resistance stability across temperature ranges and reducing PVT variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If transistors are used as resistive elements for on-chip termination, then integration is improved, but resistance varies by 10% to 60% across temperature range and exhibits non-linear IV characteristics
Solution Approach 1:
The patent changes the temperature dependence parameter of resistive elements by selecting materials with opposite temperature coefficients. The first resistive element has a positive temperature coefficient while the second has a negative temperature coefficient, and their series combination creates a net temperature coefficient near zero, achieving temperature-independent resistance without complex calibration circuits
Solution Approach 2:
The patent uses a composite structure combining two different resistive materials with opposite temperature characteristics. This composite approach allows the termination scheme to achieve both integration benefits and temperature stability by leveraging the complementary properties of the two materials
2Manufacturing precision
If elaborate PVT calibration circuits are employed to control termination resistance variations, then resistance accuracy is improved, but device complexity and layout area increase
Solution Approach 1:
The patent extracts and eliminates the complex PVT calibration circuits from the termination scheme by using inherently temperature-stable resistive elements. The solution removes the need for elaborate calibration hardware while maintaining resistance accuracy across temperature variations
Solution Approach 2:
The termination scheme is designed to be self-regulating across temperature changes. The series combination of resistive elements with opposite temperature coefficients automatically compensates for temperature variations without requiring external calibration circuits, making the system self-sufficient
3Manufacturing precision
If separate PVT calibration circuits are implemented for each voltage level and I/O bank, then impedance control accuracy is improved, but die size increases and available I/O pads decrease
Solution Approach 1:
The patent creates a universal termination scheme that works across multiple voltage levels and I/O banks without requiring separate calibration circuits. The temperature-independent resistive elements provide consistent performance across different operating conditions, allowing a single design to serve multiple functions and locations on the chip
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves substantially temperature-independent resistance and linear IV characteristics, allowing for reduced PVT variations and simplified calibration, enabling efficient and accurate impedance control with minimal layout impact.
Implementation Method 1
a first resistive element having a positive temperature coefficient of resistivity connected to a second resistive element having a negative temperature coefficient of resistivity
Data Source
AI summary
In one embodiment of the invention, an integrated circuit, such as an FPGA, has one or more programmable termination schemes, each having a plurality of resistive termination legs connected in parallel, and a calibration circuit designed to control each termination scheme for process, voltage, and temperature (PVT) variations. The sense element in the calibration circuit and each resistive leg in each termination scheme has a transistor-based transmission gate connected in series with a non-silicided poly (NSP) resistor. The negative temperature coefficient of resistivity of each NSP resistor offsets the positive temperature coefficient of resistivity of the corresponding transmission gate to provide a temperature-independent sense element and temperature-independent termination legs. The temperature-independence and constant IV characteristic of the sense element and termination legs enable a single calibration circuit to simultaneously control multiple termination schemes operating at different termination voltage levels.