On-Chip Test Controller for Field-Adaptable IC Diagnostics
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Solution Overview
Problem
Traditional in-field application tests for integrated circuit devices like SOCs and GPUs face long development cycles, high costs, and high execution latency due to fixed test patterns and algorithms, which are difficult to modify, and are unsuitable for autonomous automotive applications requiring frequent updates and on-line testing.
Innovation Solution
A hardware controller executes deterministic ATPG and x-tolerant LBIST test patterns on-chip, enabling flexible test scheduling, updates, and high diagnosis precision, with a generic design functional test architecture that focuses on functional regions, ignoring non-functional regions to save power and adapt to various SKUs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional in-field application tests utilize fixed functional patterns, then test coverage is achieved, but development cycles are long and execution latency is high
Solution Approach 1:
The patent implements dynamic test pattern generation through a hardware controller that can execute deterministic ATPG and x-tolerant LBIST algorithms on-chip. The system allows flexible test scheduling and runtime updates of test patterns, transforming the static fixed-pattern approach into a dynamic adaptive system that reduces both development cycles and execution latency while maintaining comprehensive test coverage
Solution Approach 2:
The patent replaces traditional external automatic test equipment with on-chip hardware controllers that execute test algorithms directly within the integrated circuit. This substitution eliminates the need for external testing infrastructure and enables faster test execution with reduced latency, while the deterministic ATPG and x-tolerant LBIST algorithms provide systematic fault coverage
2Adaptability or versatility
If a device is designed to support many different SKUs with configurable functional regions, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent implements a universal test architecture with hardware controllers and algorithms (deterministic ATPG and x-tolerant LBIST) that can adapt to multiple SKU configurations. The same on-chip testing infrastructure handles various functional regions and configurations through algorithmic flexibility, eliminating the need for SKU-specific test hardware and reducing overall device complexity while maintaining broad adaptability
Solution Approach 2:
The patent utilizes configurable parameters within the hardware controllers and test algorithms to adapt to different SKU configurations. By changing algorithmic parameters and test pattern characteristics rather than hardware architecture, the system achieves multi-SKU support with minimal increase in device complexity
3Use of energy by moving object
If non-functional regions are turned off to save power, then energy consumption is reduced, but test coverage of those regions is lost
Solution Approach 1:
The patent applies preliminary action by powering up non-functional regions specifically during test execution windows. The hardware controllers temporarily activate these regions only when testing is required, then power them down afterward. This time-based power management ensures complete test coverage of all regions while minimizing overall power consumption during normal operation
Data Source
AI summary
A system for testing complex integrated circuits in the field using updated tests, test sequences, models, and test conditions such as voltage and clock frequencies, over the life cycle of the circuit.