On-Chip Test Execution for Autonomous Vehicle SoCs
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Solution Overview
Problem
Traditional in-field application tests for integrated circuit devices like SOCs and GPUs face long development cycles, high costs, and execution latency due to fixed test patterns and algorithms, which are difficult to modify, and require automatic test equipment, making them unsuitable for in-system testing in autonomous automotive applications.
Innovation Solution
A system and method for on-chip execution of deterministic ATPG and x-tolerant LBIST tests, using hardware controllers to fetch and store test patterns and results, enabling flexible test scheduling and updating over the life cycle, with a design functional test architecture that focuses on functional regions, ignoring non-functional regions to reduce power consumption and logistical challenges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional in-field application tests utilize functional patterns with fixed test patterns and algorithms, then test coverage can be achieved, but development cycles are long, costs are high, and execution latency is high
Solution Approach 1:
The patent transforms static, fixed test patterns into dynamic, reconfigurable test patterns that can be modified and updated in the field. The test system allows runtime configuration of test patterns and algorithms, enabling adaptation to different SKUs and testing conditions without requiring lengthy development cycles. This dynamic approach maintains comprehensive test coverage while significantly reducing both development time and execution latency.
Solution Approach 2:
The patent enables modification of test pattern parameters and algorithms through configuration data that can be loaded onto the device. By changing test parameters dynamically rather than being fixed, the system achieves comprehensive coverage across different device configurations while reducing the need for iterative development and re-testing, thereby shortening development cycles and execution time.
2Reliability
If traditional in-field application tests require automatic test equipment, then deterministic testing can be performed, but device complexity and logistical requirements increase
Solution Approach 1:
The patent implements a self-service testing approach where the device tests itself using on-chip resources. The test system includes on-chip test pattern generators, test logic, and result analysis capabilities that eliminate the need for external automatic test equipment. This self-testing capability maintains deterministic testing reliability while dramatically reducing device complexity and logistical requirements by removing external equipment dependencies.
Solution Approach 2:
The patent creates a universal test system that can perform multiple testing functions using integrated on-chip resources. The test architecture supports various test types (logic block testing, memory testing, interconnect testing) and different test patterns within a single unified system, eliminating the need for multiple specialized external test equipment while maintaining comprehensive deterministic testing capability.
3Adaptability or versatility
If a device is designed to support many different SKUs with configurable functional regions, then adaptability increases, but test logistics become more challenging
Solution Approach 1:
The patent implements dynamic test configuration that automatically adapts to the device's SKU and operational state. The test system receives configuration data that identifies which functional regions are active in each SKU, and dynamically generates appropriate test patterns and selects relevant test logic. This dynamic adaptation maintains high adaptability across different SKUs while simplifying test logistics by eliminating the need for separate test procedures for each configuration.
Solution Approach 2:
The patent applies local quality testing by focusing test resources on the specific functional regions that are active in each SKU. Rather than testing all possible regions in all configurations, the system selectively applies test patterns to the relevant local regions based on the device's operational configuration. This approach maintains adaptability across SKUs while reducing test logistics complexity by eliminating unnecessary testing of non-functional regions.
4Productivity
If in-system tests are executed on-chip without automatic test equipment, then execution speed improves, but test pattern generation and management becomes more difficult
Solution Approach 1:
The patent prepares test patterns and configuration data in advance through automated generation tools that create compressed test images and configuration files before device deployment. These pre-generated test patterns are stored in a compact format and loaded onto the device, enabling fast on-chip execution without requiring complex runtime pattern generation. This preliminary action maintains high execution speed while managing pattern generation complexity through automated pre-processing tools.
Solution Approach 2:
The patent uses compressed representations and templates of test patterns that can be efficiently stored and replicated on-chip. Rather than storing complete, uncompressed test patterns, the system uses compact encoded representations that are decompressed and executed during testing. This copying approach enables fast on-chip execution while reducing the complexity of test pattern management through efficient compression and replication strategies.
Data Source
AI summary
Systems and methods enable the updating of tests, test sequences, fault models, and test conditions such as voltage and clock frequencies, over the life cycle of a safety critical application for complex integrated circuits and systems.