On-Chip Transaction Profiling Circuit for SoC Debugging
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Solution Overview
Problem
The integration of multiple core devices onto a single System-on-Chip (SoC) reduces the ability of external debugging tools to effectively find and solve bugs due to reduced access and increased data traffic, necessitating improved debugging technology for efficient profiling and memory usage optimization.
Innovation Solution
A method and architecture that extract transactions from interconnect circuitry, filter them using a bank of filters, increment counters based on passband matches, and output counter values to a debug controller, enabling precise and non-intrusive profiling of transactions on the integrated circuit chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If multiple core devices are integrated onto a single SoC chip, then product size is reduced and integration is improved, but access to internal buses for debugging is reduced and data traffic increases
Solution Approach 1:
The patent extracts debugging and profiling functionality from external tools and integrates it directly onto the SoC chip through on-chip debug circuitry. This allows the chip to self-monitor and self-profile without requiring external access to internal buses, resolving the contradiction between compact integration and debuggability.
Solution Approach 2:
The patent introduces an intermediary sampling circuit that periodically samples transaction data from internal buses and transfers it to external debug tools. This mediator allows external tools to indirectly monitor the chip's internal activity without direct access to the buses, maintaining both compact integration and debugging capability.
2Difficulty of detecting and measuring
If external debugging tools are used to monitor internal bus traffic, then debugging capability is provided, but access is reduced and data traffic increases making bug finding slower
Solution Approach 1:
The patent implements preliminary sampling of transaction data at periodic intervals during normal chip operation. By continuously collecting and buffering transaction information in advance, the system prepares debugging data before bugs occur, enabling faster analysis and reduction of time to detect and resolve issues.
Solution Approach 2:
The on-chip debug circuitry enables the SoC to self-monitor and self-profile its own transactions independently of external tools. The chip's internal bus traffic is automatically sampled and processed by integrated circuitry, allowing the system to provide its own debugging services without requiring external intervention for each monitoring operation.
3Measurement precision
If profiling is done by instrumenting the code, then measurement precision is improved, but the program timing is changed making the profiling intrusive
Solution Approach 1:
The patent uses an intermediary sampling circuit that passively monitors transaction data on the internal buses without inserting instrumentation into the executed code. The sampling circuit acts as a mediator that captures transaction information as it naturally flows through the bus, providing precise profiling measurements while maintaining normal program timing and avoiding the harmful intrusiveness of code instrumentation.
4Object-affected harmful factors
If profiling is done by periodic sampling, then intrusiveness is reduced, but measurement precision decreases because inter-sample behaviour is not captured
Solution Approach 1:
The patent implements continuous transaction sampling at multiple periodic intervals, maintaining continuous monitoring of bus traffic throughout the profiling period. By keeping the sampling action continuous and comprehensive across multiple cycles, the system captures both the sampled transactions and the inter-sample behavior patterns, achieving high measurement precision while maintaining low intrusiveness through passive monitoring.
Data Source
AI summary
A method of profiling transactions on an integrated circuit chip. The method comprises, for each transaction: extracting the transaction from interconnect circuitry of the integrated circuit chip; and filtering the transaction at a filtering circuit to determine which passband a parameter of the transaction lies within; sending an increment signal to a counter of a bank of counters, the counter having a counter value indicative of a number of transactions having the parameter lying within the passband; and outputting the counter values of the bank of counters.