On-Chip Transformer With Interleaved Metal Traces
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Solution Overview
Problem
Conventional on-chip transformers require significant area and increased resistance due to multiple via structures, which limits inductance per unit area and Q factor, especially in integrated circuit (IC) chips with multiple voltage domains.
Innovation Solution
The implementation of an on-chip transformer with interleaved spiral traces in multiple metal layers, where the primary and secondary inductors are formed using patterned metal traces in different layers with reduced via structures, allowing for vertical alignment and reduced resistance, thereby enhancing inductance per unit area and Q factor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional on-chip transformers are implemented with multiple via structures to connect metal layers, then the transformer can be formed with multi-layer interleaved coils, but the resistance increases and Q factor decreases
Solution Approach 1:
The patent removes unnecessary via structures from the conventional transformer design. Specifically, it eliminates vias that are not essential for the transformer operation, thereby reducing the number of via structures that contribute to resistance. This extraction of non-essential elements directly reduces energy loss and improves Q factor.
Solution Approach 2:
The patent optimizes the spatial arrangement of the transformer by implementing interleaved coil patterns across multiple metal layers. The coils are arranged to interleave in the vertical dimension (across layers) rather than requiring extensive lateral connections through vias. This dimensional reorganization reduces the need for via structures and their associated resistance.
2Reliability
If conventional on-chip transformers use multiple via structures for multi-layer connections, then the transformer can achieve multi-layer interleaved coil configuration, but the area occupied increases
Solution Approach 1:
The patent implements nested interleaved coil patterns where primary and secondary coils are interlaced across multiple metal layers. The coils are arranged in a compact nested configuration where each layer's coil pattern interleaves with adjacent layers, maximizing the use of vertical space. This nesting approach achieves high inductance per unit area without requiring excessive lateral area expansion.
Solution Approach 2:
The patent transitions from planar coil arrangements to three-dimensional interleaved patterns across multiple metal layers. By utilizing the vertical dimension (layer stacking) rather than only lateral expansion, the transformer achieves higher inductance density without proportionally increasing the chip area occupied.
3Reliability
If conventional on-chip transformers are designed with multiple via structures, then multi-layer coil connections can be established, but the device complexity increases
Solution Approach 1:
The patent extracts and removes non-essential via structures from the transformer design. By identifying and eliminating vias that are not critical for the transformer's core functionality, the design complexity is reduced while maintaining the essential multi-layer coil connections needed for transformer operation.
Solution Approach 2:
Instead of adding more via structures to achieve multi-layer connections, the patent inverts the approach by using direct planar patterns within each metal layer that achieve the desired magnetic coupling without excessive vertical interconnections. This inversion of the conventional approach simplifies the overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration achieves higher inductance per unit area and improved Q factor by reducing the number of via structures, leading to a more efficient and compact transformer design that isolates different voltage domains effectively.
Implementation Method 1
The on-chip transformer includes a primary inductor and a secondary inductor. the primary inductor is configured to have a first-primary coil portion formed of a first patterned metal trace disposed in a first metal layer and a second-primary coil portion formed of a second patterned metal trace disposed in a second metal layer
Implementation Method 2
the IC chip includes a first via structure configured to connect the first-primary coil portion formed of the first patterned metal trace in the first metal layer with the second-primary coil portion formed of the second patterned metal trace in the second metal layer
Data Source
AI summary
Aspects of the disclosure provide an integrated circuit (IC) chip with an on-chip transformer. The on-chip transformer includes a primary inductor and a secondary inductor. The primary inductor is configured to have a first-primary coil portion formed of a first patterned metal trace disposed in a first metal layer and a second-primary coil portion formed of a second patterned metal trace disposed in a second metal layer. The secondary inductor is configured to have a first-secondary coil portion formed of a third patterned metal trace that interleaves with the first patterned metal trace in the first metal layer and a second-secondary coil portion formed of a fourth patterned metal trace that interleaves with the second patterned metal trace in the second metal layer.