On-Chip Transformer With Tuning Capacitors For High Q Factor
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Solution Overview
Problem
The existing on-chip transformers in wireless communication systems face challenges in achieving a high quality factor (Q value) and minimizing structural size, leading to increased insertion loss and chip area, especially when dealing with multi-mode multi-band systems where multiple frequency bands require separate transformers, resulting in high costs and low utilization efficiency.
Innovation Solution
The solution involves arranging multiple tuning capacitors in a partially-shielded network within the blank area enclosed by the primary and secondary coils, with these capacitors connected in parallel to form an LC resonance circuit, which reduces eddy current loss and allows for a higher Q value and smaller transformer size by minimizing the area occupied by the transformer and its tuning capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the transformer coil area is reduced to minimize chip area, then the area utilization ratio is improved, but the quality factor (Q value) of the coil inductor deteriorates due to increased eddy current loss
Solution Approach 1:
The patent divides the transformer structure into multiple segments: primary coil, secondary coil, and multiple tuning capacitors arranged in a segmented manner. The tuning capacitors are divided into first tuning capacitors connected to the primary coil and second tuning capacitors connected to the secondary coil, allowing independent optimization of each segment's contribution to the overall Q value while maintaining compact area
Solution Approach 2:
The patent implements nesting by placing the first and second tuning capacitors within the blank area enclosed by the primary and secondary coils. The tuning capacitors are positioned in the space between the coils, effectively utilizing the available area without increasing the overall transformer footprint, thus improving area utilization while maintaining Q value
2Adaptability or versatility
If multiple transformers are used for multi-mode multi-band systems, then the adaptability to different frequency bands is improved, but the chip area and cost increase significantly
Solution Approach 1:
The patent creates a universal transformer structure that can operate across multiple frequency bands by incorporating adjustable tuning capacitors. The first and second tuning capacitors can be adjusted to resonate at different frequencies, allowing a single transformer to serve multiple frequency bands (e.g., 700MHz, 900MHz, 1800MHz, 2.6GHz) without requiring separate transformers for each band, thus achieving multi-functionality
Solution Approach 2:
The patent introduces dynamic adjustability through the tuning capacitors, which can be modified to change the resonant frequency of the transformer. This dynamic capability allows the transformer to adapt to different operating conditions and frequency bands, providing versatility without increasing the physical footprint by requiring multiple fixed-frequency transformers
3Area of stationary object
If the transformer area is minimized to below 400um*400um, then the chip area is reduced, but the self-inductance value becomes very small requiring large tuning capacitors
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional configuration by stacking components in multiple layers. The first tuning capacitors are positioned between the primary coil and the substrate, while the second tuning capacitors are positioned between the secondary coil and the substrate, utilizing the vertical dimension to accommodate larger effective capacitor values without increasing the horizontal footprint
4Reliability
If metal wires and components are kept far from the coil to reduce eddy current loss, then the quality factor is improved, but the transformer and surrounding blank area occupy large chip area
Solution Approach 1:
The patent introduces the tuning capacitors as intermediary elements between the coils and the substrate. These capacitors serve as mediators that allow the coils to be positioned closer to the substrate (reducing area) while the capacitors themselves provide the necessary electrical isolation and tuning function, preventing direct harmful interaction between the coil magnetic field and the substrate that would cause eddy current loss
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively improves the Q value of the transformer, reduces the chip area, and enhances the efficiency of the transformer's performance across different frequency bands, thereby addressing the issues of insertion loss and cost associated with existing on-chip transformer designs.
Implementation Method 1
these capacitors connected in parallel to form an LC resonance circuit, which reduces eddy current loss and allows for a higher Q value
Implementation Method 2
An eddy current is an induced ring current generated by a magnetic field of the inductor on a conductor
Implementation Method 3
the eddy current loss of the inductor. An eddy current is an induced ring current generated by a magnetic field of the inductor on a conductor
Data Source
Figure 1~2
Figure 3-1~4-1
Figure 4-2~4-3
AI summary
A transformer, a method for manufacturing the transformer and a chip are provided. The method includes: a first primary tuning capacitor and/or a first secondary tuning capacitor are/is arranged in an area enclosed by a primary coil and a secondary coil, wherein the first primary tuning capacitor includes more than one second primary tuning capacitor, and the first secondary tuning capacitor includes more than one second secondary tuning capacitor; the more than one second primary tuning capacitor are connected in parallel, and the more than one second secondary tuning capacitor are connected in parallel; and the more than one second primary tuning capacitor and the at least one wire between the more than one second primary tuning capacitor, and/or the more than one second secondary tuning capacitor and the at least one wire between the more than one second secondary tuning capacitor form a partially-shielded network or part of the partially-shielded network.