On-Chip Interconnect Repeaters With Transient Current-Mode Signaling
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Solution Overview
Problem
High-density interconnects in advanced chip design face bottlenecks due to non-scaling signaling interconnects, leading to reliability and performance issues per watt of power.
Innovation Solution
Implementing transient-mode current-mode signaling (CMS) mechanisms in signaling fabrics, utilizing relative timing between clock signals and adjustable delay elements to control the operational state of CMS feedback paths, allowing for efficient power management and signal integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional current-mode signaling (CMS) techniques are used, then speed is enhanced, but static (idle) power consumption increases and complex transmit/receive circuits impose large latency and area overheads
Solution Approach 1:
The patent applies dynamics by making the CMS feedback paths controllable and transient rather than static. The feedback paths are enabled only during specific time windows when signal transitions occur, and disabled during idle periods. This dynamic control allows the system to achieve CMS speed benefits during active signaling while minimizing power consumption and circuit complexity overhead during idle states.
Solution Approach 2:
The patent implements periodic action through clocked control signals that periodically enable and disable the CMS feedback paths. The feedback paths are activated during specific clock cycles when data transitions are expected and deactivated during other cycles, creating a periodic operation pattern that balances speed enhancement with power efficiency and reduced complexity overhead.
2Speed
If conventional current-mode signaling (CMS) techniques are used, then speed is enhanced, but area overhead increases due to complex transmit/receive circuits
Solution Approach 1:
The patent extracts the essential speed-enhancing function of CMS from the complex conventional transmit/receive circuits. By implementing only the necessary feedback paths with controllable switches and using existing clock infrastructure, the patent removes unnecessary circuit complexity while retaining the speed benefits of CMS signaling.
Solution Approach 2:
The patent makes the CMS feedback paths universally controllable through clock signals that can be applied across the entire interconnect fabric. The same control mechanism serves multiple functions: enabling CMS during active periods, disabling during idle periods, and coordinating across multiple signal lines, thereby reducing per-line overhead area.
3Area of stationary object
If voltage-mode signaling (VMS) is used, then area overhead is reduced, but signaling speed and power performance per watt deteriorate
Solution Approach 1:
The patent changes the signaling parameter dynamically by switching between VMS and CMS modes based on operational state. During idle periods, the system operates in VMS mode with high-impedance inputs for area efficiency. During active signaling, the system transitions to CMS mode with low-impedance feedback paths for improved power performance per watt, thereby optimizing both area and power metrics across different operating conditions.
4Productivity
If high-density interconnects are implemented, then chip functionality is enhanced, but signaling becomes a bottleneck affecting reliability and performance per watt
Solution Approach 1:
The patent implements feedback by creating controllable feedback paths in the interconnect fabric that allow signal transitions to be actively driven. This feedback mechanism compensates for signal degradation in high-density interconnects, maintaining signal integrity and reliability even as density increases. The feedback paths are activated transiently during transitions and disabled during steady states to maintain reliability while enabling high-density functionality.
Data Source
AI summary
Circuits that include one or more transmission lines to propagate a signal through a serially-arranged plurality of repeaters, and one or more control circuits to propagate control pulses to the repeaters, wherein a timing and duration of the control pulses is configured to operate the repeaters in current-mode signaling (CMS) mode during a state transition of the signal at the repeaters and to operate the repeaters in voltage-mode signaling (VMS) mode otherwise.