On-Demand IP Initialization via Stutter Power States
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Solution Overview
Problem
Conventional power management systems in integrated circuits face inefficiencies in transitioning between reduced power states due to exit latency and delays caused by saving and restoring configuration register states, particularly during short periods of component idleness, leading to suboptimal power consumption and latency in time-sensitive operations.
Innovation Solution
Implementing a power management controller (PMC) with a stutter mode that allows on-demand powering of specific circuitry within a power domain without exiting the low-power state, using a handshaking process and a display buffer threshold to manage transitions, thereby reducing exit latency and maintaining power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the system enters a reduced power state by turning off power to components, then power consumption is reduced, but exit latency increases due to saving and restoring configuration register states
Solution Approach 1:
The patent segments the power management approach by dividing the system into different power domains and introducing intermediate power states (C-states) between full active and fully reduced power states. This allows selective powering down of specific IP blocks while keeping others active, reducing the overall exit latency when exiting from reduced power states.
Solution Approach 2:
The patent implements preliminary actions by pre-saving configuration register states to memory before entering reduced power states, and pre-loading necessary configuration data. This preparation reduces the time required to restore states when exiting power states, thereby reducing exit latency.
2Reliability
If the system saves and restores configuration register states during power state transitions, then system reliability is maintained, but transition delays increase
Solution Approach 1:
The patent applies partial action by selectively saving and restoring only the necessary configuration register states for the specific IP blocks that are transitioning power states, rather than saving and restoring all system states. This reduces transition delays while maintaining reliability for the affected components.
Solution Approach 2:
The power management controller autonomously manages the saving and restoring of configuration register states without requiring external intervention. The system self-services by automatically handling state preservation and restoration, reducing manual configuration time and improving transition efficiency.
3Loss of energy
If the system transitions to reduced power states during short idle periods, then power consumption is reduced, but performance degradation occurs in time-sensitive operations
Solution Approach 1:
The patent implements dynamic power management by introducing multiple intermediate power states (C0, C1, C2, C3) that allow the system to adjust its power consumption level dynamically based on the duration and nature of idle periods. Time-sensitive operations can trigger transitions to higher performance states, while longer idle periods can utilize deeper power savings, optimizing both power consumption and performance responsiveness.
4Loss of time
If the system keeps components active during short idle periods, then exit latency is reduced, but power consumption increases
Solution Approach 1:
The patent changes the power state parameters by introducing intermediate C-states with different power consumption and exit latency characteristics. The system can select the appropriate power state parameter set based on the specific operational context, achieving a balance between power savings and exit latency reduction that neither extreme (fully active or fully reduced) can provide alone.
Data Source
AI summary
Systems, methods, and devices for integrated circuit power management. A mode of a power management state is entered, from the power management state, in response to an entry condition of the mode. A device that is otherwise powered off in the power management state is powered on in the mode of the power management state. In some implementations, the device includes a communications path between a second device and a third device. In some implementations, the device is in a power domain that is powered off in the power management state. In some implementations, the power domain is powered off in the mode. In some implementations, the device is powered on in the mode via a power rail that is specific to the mode. In some implementations, the entry condition of the mode includes an amount of data stored for display in a display buffer falling below a threshold amount.