On-Demand Memory Bank Activation for Low-Power SoCs
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Solution Overview
Problem
Existing microcontroller systems face significant power consumption issues due to all memory banks being activated even when only a subset is used, leading to inefficient energy usage and potential battery drain or heat generation.
Innovation Solution
A system-on-chip architecture with a power controller that selectively changes memory banks between power modes based on transaction requests, using voltage levels and power switches to minimize unnecessary power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all memory banks are activated to ensure data access availability, then system reliability is improved, but power consumption increases
Solution Approach 1:
The memory system is divided into multiple independent memory banks, each capable of being independently activated or deactivated. The power controller selectively activates only the specific memory bank requested by a transaction, rather than activating all banks. This segmentation allows the system to maintain data access reliability for active banks while reducing overall power consumption by keeping inactive banks in a low-power state.
Solution Approach 2:
The system dynamically adjusts the power state of memory banks based on real-time transaction requests. The power controller monitors incoming transactions and activates memory banks on-demand, transitioning them from a low-power state to an active state only when needed. This dynamic approach ensures that memory availability matches actual system needs, preventing unnecessary power consumption while maintaining reliability.
2Speed
If memory banks remain in active mode for quick access, then access speed is improved, but power consumption increases
Solution Approach 1:
The system employs periodic activation of memory banks based on transaction requests rather than continuous activation. Memory banks transition between active and low-power states in response to periodic transaction requests. This periodic action pattern allows the system to achieve fast access speeds when transactions occur while minimizing power consumption during idle periods when no transactions are pending.
3Use of energy by moving object
If power mode switching is implemented for memory banks, then power consumption is reduced, but system complexity increases
Solution Approach 1:
A power controller is introduced as an intermediary component between the transaction interface and the memory banks. This power controller monitors transaction requests and automatically manages the activation and deactivation of memory banks. By delegating power management tasks to this intermediary component, the system reduces overall power consumption while maintaining relatively simple architecture, as the power controller handles the complexity of coordinate memory bank management.
Data Source
AI summary
A low-power system-on-chip includes an originating controller, a fabric, and a power controller. The originating controller is configured to initiate a memory transaction request including a source address. The fabric includes an arbiter configured to receive the memory transaction request and determine a first memory device associated with the memory transaction request. The power controller is configured to selectively change a first memory bank of the first memory device from a first power mode to a second power mode based at least in part on the source address. The fabric is configured to perform a memory operation by (a) receiving stored data from memory storage locations corresponding to the source address when the memory transaction request includes a read request, and (b) sending data included in the memory transaction request to the memory storage locations when the memory transaction request includes a program or a write request.