On-Device Constrained Random Verification for Circuit Testing
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Solution Overview
Problem
The development of electronic circuits faces challenges in thorough verification, particularly due to the difficulty and time-consuming nature of creating directed tests to cover all variable combinations, and the cost and time constraints of using constrained random verification, leading to limited options for verifying hardware beyond corner cases.
Innovation Solution
A method involving constrained random verification functionality that automatically creates and executes random verification tests based on the hardware architecture description and constraints, using a processor and memory to generate and store input and expected output data, compare actual and expected outputs, and log inconsistencies, thereby thoroughly testing the device under test.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If directed tests are used to verify specific aspects of the device, then measurement precision is improved, but loss of time increases due to the difficulty and time-consuming nature of developing sufficient directed tests to cover all variable combinations
Solution Approach 1:
The verification system performs self-verification by executing directed tests that were automatically generated from the hardware architecture description. The device under verification executes its own verification protocols without requiring external test equipment, thereby reducing verification time while maintaining precision through comprehensive directed test coverage
Solution Approach 2:
Directed tests are generated in advance from the hardware architecture description before the actual verification process. This preliminary generation of comprehensive test cases ensures that all variable combinations are covered without requiring time-consuming manual test development during the verification phase
2Productivity
If constrained random verification is used to generate random verification tests, then productivity is improved, but loss of time increases due to the cost and time constraints of running constrained random verification
Solution Approach 1:
The verification process is segmented into two distinct phases: directed verification for thorough testing of specific aspects, and constrained random verification for efficient exploration of the design space. This segmentation allows each method to be applied where it is most effective, optimizing both productivity and time utilization
Solution Approach 2:
The system performs more verification than traditionally required by combining both directed and constrained random verification approaches. The directed tests provide exhaustive coverage of critical paths while constrained random tests provide additional coverage of edge cases, achieving superior verification without excessive time cost
3Reliability
If comprehensive directed tests are developed to cover all variable combinations, then reliability is improved, but device complexity increases due to the complexity of managing and executing extensive test suites
Solution Approach 1:
An automated test generation system acts as an intermediary between the hardware architecture description and the verification process. This intermediary automatically generates, manages, and executes comprehensive directed tests based on the architecture description, thereby achieving high verification reliability without the complexity of manual test suite management
4Manufacturing precision
If verification is performed on physical devices after fabrication, then manufacturing precision is improved, but loss of time increases due to the difficulty of monitoring electronic signals in physical devices compared to simulation models
Solution Approach 1:
The system replaces complex physical signal monitoring with automated digital verification executed directly on the physical device. By using the device's own processor to execute verification algorithms and monitor its own signals, the system achieves manufacturing precision verification without the time-consuming overhead of external physical measurement equipment
Data Source
AI summary
A method of functionally verifying a device under test having at least one processor and at least one memory is disclosed. The method includes creating verification data for the device under test using a constrained random verification data creation process executed on the at least one processor. The verification data includes input data and expected output data. The method further includes storing the verification data in the at least one memory. The method further includes processing the input data with the at least one processor to produce actual output data. The method further includes comparing the actual output data to the expected output data. When the actual output data does not equal the expected output data, the method further includes storing at least one inconsistency between the actual output data and the expected output data.