On-Die ECC Circuit Layout Reduction in Data Receiving Terminals
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Solution Overview
Problem
Existing data error correction circuits in integrated circuits require numerous circuit elements and occupy large layout areas, necessitating redundant error correction processes in data receiving terminals.
Innovation Solution
Implementing an On Die ECC circuit in the memory to generate a second check code based on the first data and check code, allowing direct error correction and check code generation in the memory, reducing the need for additional circuit elements and layout area in the data receiving terminal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a link ECC is implemented in the data receiving terminal to perform error correction on received data, then error correction accuracy is improved, but the number of circuit elements and layout area increase
Solution Approach 1:
The patent extracts the error correction function from the data receiving terminal and relocates it to the memory device. The memory device generates a second check code including a full check value based on the transmitted data, and performs error correction before outputting the corrected data. This extraction removes the need for complex ECC circuits in the receiving terminal while maintaining error correction capability.
Solution Approach 2:
Instead of having the receiving terminal perform error correction on received data (conventional approach), the patent inverts the approach by having the transmitting memory device perform error correction on the data before transmission. The receiving terminal only needs to receive the already-corrected data and the corresponding check code, significantly reducing its circuit complexity.
2Reliability
If a link ECC is implemented in the data receiving terminal to perform error correction on received data, then error correction accuracy is improved, but the layout area increases
Solution Approach 1:
The patent extracts the error correction function from the data receiving terminal and relocates it to the memory device. The memory device generates a second check code including a full check value based on the transmitted data, and performs error correction before outputting the corrected data. This extraction removes the need for complex ECC circuits in the receiving terminal while maintaining error correction capability.
3Reliability
If the full check value is generated according to each bit of the data and each bit of the first check code in the data receiving terminal, then error correction accuracy is improved, but the requirement on circuit functions increases
Solution Approach 1:
The patent applies preliminary action by having the memory device generate the second check code including the full check value before data transmission. The full check value is calculated based on the data bits and first check code bits in advance at the transmitting end. This preliminary generation of check codes simplifies the receiving terminal's circuit requirements, as it only needs to receive and process the pre-generated check codes without performing complex full check value calculations.
Data Source
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AI summary
Provided are a data error correction circuit and a data transmission method. The data transmission circuit includes: a data error correction module, configured to receive first data and a first check code corresponding to the first data, perform error correction on the first data according to the first check code to generate second data, and output the second data; and a check code generation module, configured to receive the first data and the first check code, generate a second check code according to the first data and the first check code, and output the second check code. Embodiments of the disclosure can reduce elements and a layout area required by a data error correction function.