On-Die ECC Memory Architecture for Pattern Noise and Read Latency
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Solution Overview
Problem
As semiconductor memory devices, such as DRAMs, undergo scaling, their capacitance decreases, leading to noise issues due to repeated data patterns, which affects their operating characteristics and requires additional logic for data scrambling, increasing latency and circuit size.
Innovation Solution
Incorporating an on-die error correction code (ECC) engine that scrambles main data with a random binary code during write operations and performs ECC encoding, allowing for parallel ECC decoding and syndrome generation during read operations to correct errors without additional scrambling, thus reducing latency and logic size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If data scrambling is performed using separate logic circuitry, then pattern noise is reduced, but latency increases and circuit size increases
Solution Approach 1:
The patent combines the data scrambling function with the ECC engine into a single integrated circuit. The ECC engine performs both error correction encoding and data scrambling using shared hardware resources, eliminating the need for separate scrambling logic. This integration reduces the overall circuit size and allows scrambling operations to be performed in parallel with ECC operations, thereby reducing latency while still effectively reducing pattern noise.
Solution Approach 2:
The ECC engine is designed to perform multiple functions: error correction encoding, data scrambling, and syndrome calculation. By making the ECC engine universal and multi-functional, the patent eliminates dedicated scrambling circuitry, reduces circuit complexity and size, and enables parallel processing of multiple operations to reduce latency.
2Object-affected harmful factors
If data scrambling is performed using separate logic circuitry, then pattern noise is reduced, but circuit size increases
Solution Approach 1:
The patent merges the data scrambling function with the ECC engine into a single integrated unit. The ECC engine uses shared hardware resources to perform both error correction and scrambling operations, eliminating redundant logic circuitry. This integration significantly reduces the overall circuit size and complexity while maintaining effective pattern noise reduction.
Solution Approach 2:
The ECC engine is designed as a universal block that performs multiple functions including error correction encoding, data scrambling, and syndrome calculation. This multi-functionality eliminates the need for separate dedicated scrambling logic, thereby reducing circuit complexity and size without compromising the ability to reduce pattern noise.
3Quantity of substance
If capacitance is decreased due to scaling, then integration density increases, but noise occurs due to repeated data patterns
Solution Approach 1:
The patent applies data scrambling as a preliminary action before storing data in the memory cell array. By scrambling the data patterns before they are written to the scaled memory cells, the system prevents the formation of repetitive patterns that would cause noise. This preliminary scrambling action allows the memory to achieve high integration density through scaling while maintaining signal quality by eliminating pattern-related noise.
Data Source
AI summary
A semiconductor memory device includes a memory cell array and an on-die error correction code (ECC) engine. The on-die ECC engine, during a write operation, generates a second main data by encoding a first main data with a random binary code, performs an ECC encoding on the second main data to generate a parity data and stores the second main data and the parity data in a target page in the memory cell array. The on-die ECC engine, during a read operation, reads the second main data and the parity data from the target page, performs an ECC decoding on the second main data based on the parity data to generate a syndrome in parallel with generating the first main data by encoding the second main data with the random binary code and corrects at least one error bit in the first main data based on the syndrome.