On-Die ECC Validation via Controlled Error Injection
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Solution Overview
Problem
Current methods for validating on-die error correction code in computer memory, particularly for double bit errors, are inadequate as they lack precise control and accuracy, leading to potential silent data corruption due to misinterpretation of errors by the CPU.
Innovation Solution
A method that allows controlled injection of known errors into the memory array by disabling the generation of new ECC check bits during a write cycle, enabling precise validation of on-die ECC logic without modifying existing ECC data, thereby ensuring accurate detection and correction of single and double bit errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If on-die ECC logic is used to correct errors in real-time, then data integrity is improved, but the ability to validate ECC operation through direct data modification is blocked
Solution Approach 1:
The patent applies preliminary action by disabling ECC code generation before data writing, creating a controlled state where data can be modified without triggering automatic ECC recalculation. This allows validation operations to be performed on the memory array while maintaining the original ECC codes, thereby enabling validation capability without compromising the normal data integrity protection when ECC is enabled.
Solution Approach 2:
The patent introduces an intermediary validation mode that mediates between the need for data integrity (ECC enabled) and validation capability (direct modification). In this mode, the system temporarily disables ECC generation only for validation operations, allowing direct data modification and error injection, then restores normal ECC operation afterward. This intermediary state enables validation without permanently sacrificing data integrity protection.
2Reliability
If ECC code generation is enabled during data writing, then data integrity is maintained, but precise error injection for validation cannot be achieved
Solution Approach 1:
The patent applies preliminary action by disabling ECC code generation before data writing, creating a controlled state where data can be modified without triggering automatic ECC recalculation. This allows validation operations to be performed on the memory array while maintaining the original ECC codes, thereby enabling validation capability without compromising the normal data integrity protection when ECC is enabled.
Solution Approach 2:
The patent changes the operational parameter of ECC code generation from enabled to disabled during validation operations. This parameter change allows the system to transition from a state where ECC automatically corrects errors (compromising validation) to a state where errors can be precisely injected and observed (enabling validation), with the ability to restore the original parameter afterward.
3Ease of operation
If direct modification of stored data is allowed, then validation of ECC operation becomes possible, but data integrity protection is compromised
Solution Approach 1:
The patent applies dynamics by making the ECC code generation capability dynamic rather than static. The system can switch between enabled and disabled states based on operational needs: enabled during normal operation for data integrity protection, disabled during validation operations for direct data modification. This dynamic control resolves the contradiction by allowing both data integrity protection and validation capability at different times.
Solution Approach 2:
The patent implements periodic action through alternating between normal operation mode (ECC enabled for data integrity) and validation mode (ECC disabled for direct modification). This periodic switching allows the system to maintain data integrity protection during normal operations while periodically enabling validation operations, thereby achieving both goals through time-based separation.
Data Source
AI summary
Embodiments are generally directed to validation of memory on-die error correction code. An embodiment of a memory device includes one or more memory arrays for the storage of data; control logic to control operation of the memory device; and ECC (error correction code) logic, including ECC correction logic to correct data and ECC generation logic to generate ECC code bits and store the ECC bits in the one or more memory arrays. In a validation mode to validate operation of the ECC logic, the control logic is to allow generation of ECC code bits for a first test value and disable generation of ECC code bits for a second test value.